Principal System Validation Engineer Serdes Jobs - Hiro
Browse 38+ Principal System Validation Engineer Serdes roles from companies hiring right now. Updated daily as new jobs land on Hiro. Salaries range from $0K to $0K based on listed pay.
38 Principal System Validation Engineer Serdes roles
Sorted by most recently posted.
Director, High Speed SerDes Application Engineering
Marvell · CA Santa Clara
Hardware Validation Engineer - High-Speed Interfaces (Optics, SERDES, Signal Integrity, Automation/AI) (4 to 8 Years)
Cisco · Bangalore, India
SerDes Micro Architect
Apple · Beaverton, OR
Principal Engineer - Verification / AMS / SerDes
Marvell · Bangalore, India
Senior Silicon Validation Engineer (High-Speed SerDes)
Marvell · Santa Clara, CA
Senior Staff Analog Circuit Design Engineer - SerDes
Intel · Virtual, Canada
Layout Design Engineer II (SerDes)
Cadence · Cork 01
High Speed SerDes DSP RTL Designer
Broadcom · Usa-california-san Jose-1320 Ridder Park Drive
$120K–$192K/yr
Analog Engineer - SerDes Compliance
Ciena · Ottawa, Canada
$114K–$182K/yr
Principal SerDes System/DSP Design Engineer
Ciena · Ottawa, Canada
$126K–$202K/yr
Digital Senior SerDes Design Engineer
Ciena · Ottawa, Canada
$109K–$174K/yr
Sr Application Engineer - SerDes Design IP
Cadence · San Jose
$103K–$191K/yr
Principal Analog IC Design Engineer, High Speed SerDes
Cadence · San Jose
$137K–$254K/yr
Senior Serdes System Design Engineer/Architect
Broadcom · Usa-tx-austin - River Place B7
$108K–$192K/yr
Digital Design: SerDes Digital IP Design Engineer
Broadcom · Usa-colorado-fort Collins-4380 Ziegler Road
$127K–$203K/yr
Senior SerDes System Engineer
Altera · Haifa, Israel
Head of Program & Portfolio Management - SerDes Networking Solutions
Nxp Semiconductors · San Jose (rose Orchard)
$220K–$303K/yr
Principal SerDes Validation Engineer
Marvell · Santa Clara, CA
Senior Manager, Serdes Analog Design
Samsungsemiconductor · San Jose, CA
SIPI Architect for High-Speed SerDes
Apple · Emeryville, CA
SIPI Architect for High-Speed SerDes
Apple · Emeryville, CA
SIPI Architect for High-Speed SerDes
Apple · Emeryville, CA
SIPI Architect for High-Speed SerDes
Apple · Emeryville, CA
Analog Design Engineer - SerDes
Olix · Austin
SerDes Micro Architect
Apple · Cupertino, CA
Layout Design Engineer II (SerDes)
Cadence · Cork, Ireland
SerDes Circuit Design Engineer
Apple · Beaverton
SerDes System Validation Engineer
Apple · Cupertino
AMS SerDes Robustness Analysis Validation Architect
Apple · Emeryville, CA
Analog/Mixed-Signal Engineer - SerDes (PhD Intern 2026)
Asteralabs · Irvine, CA
Analog/Mixed-Signal Engineer - SerDes
Asteralabs · Singapore, Singapore
SerDes Micro Architect
Apple · San Diego, CA
SerDes Circuit Design Engineer
Apple · Cupertino
Principal Silicon Validation Engineer, SerDes/PAM4
Asteralabs · San Jose, CA
Sr. SI/PI Engineer - Serdes, Satellites (Starlink)
Spacex · Sunnyvale, CA
Principal System Validation Engineer - SerDes/Ethernet (PAM4)
Asteralabs · San Jose, CA
Senior SerDes Architect and Lead
Omnidesigntech · Milpitas
Senior SerDes Analog Design
Omnidesigntech · Milpitas
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