Design Verification Engineering Manager

Responsibilities

• Lead, build, and technically mentor a verification team operating with high autonomy; set clear goals, remove blockers, drive accountability, and maintain a flat, execution-focused culture
• Own end-to-end verification strategy across coherent interconnect IP, protocol bridges, and fabric subsystems from architecture engagement through coverage closure and silicon signoff
• Stay hands-on: review testplans, debug critical protocol issues, make architecture-level verification calls, and write code when it unblocks the team
• Drive verification methodology for cache coherency protocols, memory ordering models, and multi-die link-layer transports; ensure coverage models capture real system corner cases
• Collaborate directly with architecture, RTL design, physical design, and post-silicon teams; resolve cross-team technical conflicts quickly and with data
• Establish delivery cadence, risk frameworks, and quality metrics that give the team and stakeholders predictable visibility into milestone health
• Recruit and develop senior technical talent; build a bench that can independently own complex IP verification with minimal oversight
• Evaluate and integrate emerging verification approaches including formal, emulation, and ML-driven stimulus generation into a unified closure strategy

Requirements

• BS/MS in Electrical Engineering, Computer Science, or related field, with 20+ years of progressive experience in design verification and verification leadership
• Deep expertise in cache coherence protocols and memory consistency models (MOESI/MESI variants, directory-based and snoop-filter coherence, ordering rules across agents); hands-on experience verifying coherent fabrics or CPU cache subsystems
• Strong architectural understanding of modern CPU microarchitectures, multi-level memory hierarchies, and system-level address translation (MMU/IOMMU)
• Proven experience with chiplet-scale and die-to-die interconnects (UCIe, CXL, or proprietary D2D links), including link-layer credit management, retry, and flit-level protocol verification
• Broad protocol fluency across AMBA CHI, ACE, AXI, PCIe/CXL, and related on-die and off-die fabrics
• Strong background in simulation and formal verification methodologies including UVM, SVA, and co-simulation; working knowledge of emulation-based verification approaches
• Hands-on coding proficiency in SystemVerilog/UVM, C/C++, and Python; comfort using AI-assisted development tools as part of everyday workflow
• 5+ years demonstrated success building, leading, and scaling verification teams; track record of shipping high-quality silicon on predictable schedules
• Excellent communication skills; able to operate with minimal direction, make fast decisions with incomplete data, and drive a team that does the same
• Experience leading geographically distributed teams with a lean, high-trust operating model
• Prior exposure to network-on-chip architectures, QoS arbitration schemes, and fabric-level power management verification
• Background in formal verification tools (JasperGold, VC Formal) applied to coherence and protocol checking at scale
• Familiarity with RTL design, physical design constraints, and CAD flows; enough to make architecture-level trade-offs that account for implementation cost
• Track record of building verification IP or methodology that shipped across multiple product generations
• Job Type:
• Experienced Hire
• Shift:
• Shift 1 (India)
• Primary Location:
• India, Bangalore
• Additional Locations:
• Business group:
• Posting Statement:
• All qualified applicants will receive consideration for employment without regard to race, co

Benefits

Additional Information

Job Details: Job Description: Job Description Intel is seeking a Design Verification Manager for the Silicon Chassis team. In this player-coach role, you will lead a high-autonomy verification team while staying technically deep, driving verification strategy and hands-on execution for next-generation interconnect and coherent fabric IP. You will build and scale a team with a startup operating model inside Intel, owning everything from architecture trade-offs through silicon signoff. This role requires 20+ years of accumulated expertise in coherent interconnects, processor microarchitecture, memory hierarchies, and die-to-die communication, combined with a proven ability to attract, develop, and ship through strong technical teams. AI-assisted workflows are part of everyday development here.

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Company Intel

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