Failure Analysis Engineer, Microelectronics (Starlink)

Responsibilities

• Own end-to-end root cause failure analysis investigations on microelectronics failing in manufacturing, test, and field, from initial failure characterization through final corrective action verification
• Conduct advanced electrical fault isolation and characterization using curve trace, TDR, RF characterization, Lock-in Thermography, OBIRCH, EBIRCH, EBAC, nanoprobing, and related techniques to precisely localize defects in complex devices
• Perform advanced physical failure analysis using SEM, FIB, EDS, SAM, cross-sectioning, and related techniques to identify failure mechanisms in silicon, packaging, and interconnects
• Apply physics-of-failure principles and deep knowledge of semiconductor failure modes (electromigration, thermal fatigue, delamination, EOS/ESD, solder joint fatigue, etc.) to determine root causes
• Drive corrective actions by working directly with silicon design, packaging, and manufacturing teams to implement and validate design or process changes based on FA findings
• Author detailed technical reports documenting failure modes, root cause conclusions, supporting data, and corrective action effectiveness
• Develop and improve failure analysis techniques and workflows to support new packaging technologies and advanced materials

Requirements

• Bachelor's degree in materials science, electrical engineering, physics, chemical engineering, or other STEM discipline
• 2+ years of hands-on experience in microelectronics failure analysis or materials characterization (internship experience is applicable)
• PREFERRED SKILLS AND EXPERIENCE:
• Master's or PhD in materials science, electrical engineering, physics, chemical engineering, or other STEM discipline with a focus on microelectronics or failure analysis
• Direct experience with failure analysis tools and techniques (SEM, FIB, EDS, cross-sectioning, fault isolation, or equivalent)
• Strong understanding of semiconductor physics and common microelectronics failure mechanisms (electromigration, thermal fatigue, delamination, solder joint fatigue, electrical overstress/ESD, etc.)
• Proficiency with advanced FA tools including SEM, FIB, SAM, and EDS
• Hands-on experience in electrical characterization and fault isolation techniques such as IV curves, RF/VNA measurement, LIT, OBIRCH, EBIRCH, EBAC, nanoprobing, photon emission, or voltage contrast
• Experience applying JEDEC and AEC reliability test standards and physics-of-failure methodologies to root cause investigations
• Experience analyzing complex datasets with Python, JMP, or similar tools
• Excellent problem-solving, communication, and technical writing skills
• ADDITIONAL REQUIREMENTS:
• Ability to work overtime and weekends as needed
• Ability to work in a cleanroom or ESD-controlled environment when required
• ITAR REQUIREMENTS:
• Applicants wishing to view a copy of SpaceX's Affirmative Action Plan for veterans and individuals with disabilities, or applicants requiring reasonable accommodation to the application/interview process should reach out to EEOCompliance@spacex.com .

Additional Information

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. FAILURE ANALYSIS ENGINEER, MICROELECTRONICS (STARLINK) Starlink is SpaceX's ambitious goal to bring high-quality internet to the globe by building a constellation of thousands of satellites in low Earth orbit (LEO) using our Falcon 9 and Starship reusable rockets. We are developing millions of devices for end users to link our customers to our satellites. As a Failure Analysis Engineer on the Starlink team, you will perform detailed root cause failure analysis on microelectronic components and packaging to support high-volume manufacturing, qualification, and field returns. You will leverage advanced laboratory tools and physics-of-failure techniques to identify failure mechanisms and drive corrective actions that improve the reliability of our satellite constellation and user terminals.

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