Staff Verification Engineer- PCIe/UALink/CXL

Requirements

• Bachelor's degree in Electrical Engineering or related fields and 5 years of design verification experience.
• Master's degree in Electrical Engineering or related fields with 3 years of design verification experience
• Hands-on experience on using Verilog, System Verilog and UVM (Universal Verification Methodology)
• Good scripting skills in languages such as Perl, Tcl, or Python.
• Experience in PCIe and CXL is a plus
• Good verbal and written communication skills in English
• Additional Compensation and Benefit Elements
• All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
• Interview Integrity
• To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.
• #LI-RV1

Additional Information

About Marvell Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Marvell's Optical and Copper Connectivity Business Unit is the industry leading provider of infrastructure solutions to enterprise, data center, service providers, small business, and digital home customers. The HSC team is a key part of Optical and Copper Connectivity Business Unit that creates Marvell's high-speed copper PHY/Retimer products. At Marvell, everyone has an important role to play in changing the way tomorrow's enterprise, cloud, automotive, and carrier architectures transform-for the better. We move, store, process and secure the world's data with semiconductor solutions designed for our customers' current needs and future ambitions. What You Can Expect What You Can Expect Develop and maintain verification environment in UVM (Universal Verification Methodology) Define and review verification test plan with architecture team and design team Verify the design with directed and constraint random functional parameters Maintain regression and debug test failures with designers Report and analyze verification coverage of design features and parameters Drive the verification to reach coverage target Take responsibility in the verification of blocks, sub-systems and top-level environment.

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