Senior FPGA/Emulation Validation Engineer

Responsibilities

• Help set up FPGA/Emulation platform and device modeling
• Help set up FPGA/Emulation debugging tools
• Help customize the SOC design for the FPGA/Emulation platform
• Duties include modeling, debugging, creating and running validation tests, as well as supporting SW debugging
• Work with SOC design engineers, verification, systems and software team to achieve pre-silicon emulation and prototyping goals
• Strong experience working with FPGA and Emulation platforms. Familiarity with PCIe, USB, Ethernet, SPI and other commonly used protocols in SOC ASIC designs
• Strong experience working with FPGA tools likes Vivado
• Good knowledge of how FW/SW works on SOC
• Good communication skills
• BS or MS (preferred) degree in EE/EECS/CS or equivalent.
• 5 plus years of work experience
• Compensation Range - $80,000 - $200000
• Axiado is committed to attracting, developing, and retaining the highest caliber talent in a diverse and multifaceted environment. We are headquartered in the heart of Silicon Valley, with access to the world's leading research, technology and talent.

Additional Information

The Senior FPGA/Emulation Validation Engineer position is your opportunity to join one of the industry's leading companies in platform security management and ransomware detection for cloud datacenters, 5G infrastructure and disaggregated compute ecosystems. You should have prior knowledge about SOC architecture, and emulation and prototyping platforms. As the Senior FPGA or Emulation Validation Engineer for Axiado, you will have the opportunity to work in design verification, debug and system integration. You will work closely with the Architecture, Verification, ASIC Design and Software teams.

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Company Intel

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