Fe Cpie Pi Mts

Requirements

• 7+ years of experience in process related role in semiconductor industry.
• Bachelors/Masters/PhD. in EE, Materials Engineering, Materials Science, Physics and Chemical
• Good model based problem solving together with data driven decision making, and presentation skills.
• Proven track record to fix and tackle structure and device related issues, and address root cause.
• Good organizational capabilities and ability to work effectively. Ability to be flexible with job responsibilities and take the initiative to assume added responsibilities. Travel to Micron sites as vital for face to face collaboration.
• Strong interpersonal skills and customer/co-worker relationships. Successfully demonstrated teamwork skills with a strong focus on developing good team dynamics.
• Good multi-tasking, verbal and written communication skills.
• Ability to apply baseline digital fluency and role‑appropriate AI literacy to use AI‑enabled tools responsibly and effectively for research, analysis, content creation, problem‑solving, operational tasks, and achieving business outcomes

Additional Information

Frontend Central Product Integration Engineering team strives to deliver leading edge process capability, best-in-class bits per wafer (Yield) with highest quality and fastest speed through innovation and collaboration with cross functional team. With the diversity of technology in DRAM/NAND and geography (TD development sites - Boise/Japan, 5 manufacturing sites - US (F6, ID1), Taiwan (OMT), Japan (F15) and Singapore (F10)), Frontend Central PIE team will be responsible to identify best-known-method holistically, align best-known-method timely and implement improvement systematically across the network. As FE Central Process Integration Senior Engineer, you will be responsible to develop best optimum process to achieve product maturity. Responsibilities and Tasks: Drive best-in-class product maturity which includes bits per wafers (yield), product grades (Repair Density and DPM) at the fastest speed and cycle of learning. In depth knowledge of processes across different loops or functions (FEOL, MOL, CELL, BEOL) to identify best optimum process integration solution to achieve the goal, knowledge on product and circuit design will be plus. Collaborate with YE, Device, RDA, Metrology team to resolve top yield issues, develop inline visibility to enable fast yield ramp and minimize excursion. Identify best known method and business process from DRAM/NAND sites and drive for alignment and standardize across network. Travel to Micron sites as necessary for face to face collaboration. Integrates AI-assisted tools and insights into daily work to improve efficiency, quality, or effectiveness, exercising sound judgment and complying with organizational standards and legal requirements. Contributes to a culture of continuous improvement by identifying, testing, and sharing AI-enabled enhancements within one's scope of work.

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Company Intel

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