Principal Engineer, ASIC Verification & Validation Engineering

Requirements

• Education: BS or MS in Electrical Engineering, Computer Engineering, or Computer Science.
• Experience: 8-15 years of experience working in or around pre-silicon development, hardware verification, or platform bring-up.

Benefits

Additional Information

Role Overview The Platform Engineering organization is looking for a self-driven, hands-on engineer who can bridge the communication and skillset divide between firmware, silicon design, and hardware validation. Your primary responsibility will be supporting our advanced prototyping and emulation platforms, with a specific focus on end users. The ideal candidate has a broad, systems-level knowledge base, with deep technical expertise in platform bring-up, hardware/software co-verification, and high-density FPGA deployments. Duties and Responsibilities Lead Project Bring-Up & Diagnostics: Partner with firmware and hardware teams during the critical early phases of project bring-up. Own the initial setup, environment configuration, and stabilization of emulation and prototyping platforms. Triage & Debug: Act as the first line of defense for complex system-level failures during bring-up. Rapidly isolate root causes across the hardware, FPGA/emulator configuration, and early boot-code boundaries. Partner with Customers: Work directly with product firmware engineers to break down execution barriers, unblock their development pipelines, and abstract away hardware complexities. Infrastructure Automation: Develop automation, monitoring scripts, and health-check reporting to maximize the reliability, utilization, and throughput of the emulation and prototyping farm. Knowledge Sharing: Document creative workarounds, capture debug methodologies, and build standardized playbooks for platform setup and troubleshooting. Desired Skills & Experience FPGA Prototyping & Support: Proven experience supporting large-scale FPGA prototyping platforms (e.g., Synopsys HAPS, custom multi-FPGA boards). Understanding of FPGA synthesis, place-and-route constraints, and clocking strategies is highly valued. System-Level Debugging: Mastery of debugging tools and protocols (e.g., JTAG, protocol analyzers, logic analyzers, in-circuit emulators) to trace signals and state machines during early platform bring-up. Emulation Platforms: Familiarity with hardware emulation architectures (e.g., Cadence Palladium, Synopsys ZeBu) and how to map design code into an emulation environment. Hardware/Firmware Intersection: Solid understanding of the firmware development lifecycle and how it intersects with ASIC development, hardware description languages (Verilog/SystemVerilog), and FPGA design. Python Expertise: Advanced Python scripting skills to develop internal tools, parsing utilities for debug logs, and automated regression testing frameworks. Rudimentary Firmware Skills: Ability to write and debug low-level diagnostic code or bare-metal software to validate platform functionality, without needing to own the production product firmware. Systems Administration: Functional understanding of networking, UNIX/Linux, and Windows administration. Because the team manages a high volume of specialized prototyping seats, the ability to troubleshoot local environment, licensing, and OS-level issues is critical. Data Manipulation: Expertise in processing and analyzing usage metrics to optimize resource allocation across a global infrastructure.

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Company Intel

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