ASIC Analog Layout Engineer (m/f/d) - REF5390S

Responsibilities

• Drive the top-level layout integration of analog/mixed-signal chips (analog on top)
• Define toplevel floorplan, padframe design and bonding diagrams in coordination with other domains
• Coordinate with other layouters to define floorplans according to the chip top level
• Generate and integrate analog layouts at block and chip level
• Perform pin placement, parasitic extraction, and layout optimization
• Ensure compliance with DRC, LVS, and support tape-out activities
• Collaborate with design engineers to meet speed, area, power, DFM, ESD, and EMC requirements
• Academic degree in Electronics Engineering or related field
• Extensive professional experience in analog layout design
• Proven experience in top-level layout integration
• Strong expertise in BCD technologies (65nm to 180nm)
• Deep understanding of deep submicron effects (parasitics, coupling, matching)
• Proficient in layout tools for design, DRC, LVS, and extraction
• Knowledge of analog circuit design
• Fluent English language skills (both written and spoken), German language skills are a plus
• Applications from severely handicapped people are welcome.
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Additional Information

As an ASIC Layout Engineer (m/f/diverse) for AESS (Advanced Electronics & Semiconductor Solutions), you will be responsible for the top-level integration of analog and mixed-signal ICs. You will drive the layout development process, ensuring robust, DRC-compliant designs with optimal area utilization. You will collaborate closely with analog circuit designers and other layout engineers to deliver high-quality silicon.

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Company Intel

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