Compute Verification Lead

Requirements

• 8+ years of silicon verification experience, including at least one tapeout owning a block's or subsystem's verification - concept-to-silicon experience driving verification from an architecture and/or design specification to production silicon
• Strong software aptitude , with proven experience crossing language boundaries while driving verification goals - comfortable working across Rust, Python, and C/C++ as the task demands
• Deep, hands-on expertise in conventional verification - SystemVerilog/UVM , assertion-based verification - with comfort across both formal and simulation-based verification
• Able to lead across methodologies : you can guide engineers in conventional silicon verification and in Rust-based SW-silicon co-simulation, and set strategy that applies each where it fits
• Either prior experience verifying designs expressed in abstracted / high-level HDLs (Bluespec, Chisel, etc.), or the ability to ramp quickly on Bluespec and drive verification strategy for designs written in it
• Strong leadership and communication - you drive sign-off conversations, mentor engineers, and partner cleanly across architecture, design, SoC, and software
• Bonus Points If You Have
• 10+ years of silicon verification experience
• Experience with the numerics of compute / matrix / vector-math datapaths (floating-point pipelines included) - enough to hold substantive conversations with architects
• Production Rust experience, or experience standing up Rust-based co-simulation / co-verification flows
• Hands-on experience in an abstracted / functional HDL ecosystem (Bluespec BH/BSV, Chisel, etc.)
• Familiarity with emulation and prototyping platforms; participation in silicon debug and bring-up
• Background in AI accelerator, GPU/TPU-class, or other high-throughput compute datapath verification

Benefits

Additional Information

What MatX Is Building MatX is on a mission to be the compute platform for AGI. We are developing vertically integrated full-stack solutions from silicon to systems including hardware and software to train and run the largest ML workloads for AGI. MatX is seeking silicon micro-architects and design engineers to join our team as we create best-in-class silicon for high-performance and sustainable GenAI. Successful candidates for these roles will be responsible for delivering performant and functionally accurate silicon for MatX products across compute, memory management. High-speed connectivity and other key technologies. This is a senior, hands-on individual-contributor (IC) technical leadership role . You will own the verification strategy for the compute datapath and drive it across two complementary worlds: conventional silicon verification (SystemVerilog/UVM, assertion-based, formal) and Rust-based software-silicon co-simulation . You will set direction, raise the bar on quality and coverage, and provide technical guidance to verification engineers working in both styles - including early-career engineers growing into independent owners. What You'll Do Here Own and drive the end-to-end verification strategy - across block, subsystem, and SoC levels - spanning conventional (UVM/SV, assertion-based, formal) and Rust SW-silicon co-simulation approaches Provide technical direction and mentorship to verification engineers working in both conventional silicon-verification and Rust co-simulation roles; grow early-career engineers into independent owners of their areas Make and own the methodology calls - where conventional UVM/SV, Rust co-simulation, and formal each fit best - and drive verification strategy accordingly Drive verification across the seams: partner with SoC integration, formal verification , and the software/modeling team to turn architectural specifications into concrete, testable properties and coverage closure Plan and drive intermediate and sign-off reviews on test plans, execution progress, and verification closure toward design freeze and tapeout Build and curate verification infrastructure and regressions the broader team can adopt and extend

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Company Intel

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