Mixed Signal IP Verification Engineer

Requirements

• Candidate must possess a BS, MS degree with 3+ years of relevant industry experience in Design verification, System Verilog and OVM/UVM.
• Candidate must be experienced in validation flow right from testbench architecture and test plan creation to verification closure, waveform debug, functional coverage, code coverage, VCS NLP and non-NLP simulations and GLS
• Capable of multitasking in dynamic environment with multiple teams from different geos
• Solid verbal and written communication skills
• Excellent debug and problem solving skills
• Knowledge of DDRPHY validation with good hold on DFx features
• Good scripting skills in Python/Perl
• Exposed to Git version control
• VSCode GitHub CoPilot or any other AI experience
• Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.
• Job Type:
• Experienced Hire
• Shift:
• Shift 1 (India)
• Primary Location:
• India, Bangalore
• Additional Locations:
• Business group:
• Posting Statement:
• Position of Trust
• N/A
• Work Model for this Role
• This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
• *

Benefits

Additional Information

Job Details: Job Description: The Memory PHY Group (MPG) within the Central Engineering Group (CEG) is looking for a Pre-Silicon Verification Engineer to deliver latest and best-in-class DDR PHY IP for SoCs across Intel for the latest desktop, laptop, and other products. In this role you will perform all aspects of the functional verification flow to ensure design will meet specification requirements. You will perform IP Verification related tasks such as creating test plan, defining TB architecture and creating test benches, validating design and micro-architectural implementation. You will be automating validation tasks to drive efficiency. You will be analyzing results and help to debug issues in pre-silicon environment at IP, subsystem and SOC level. You will collaborate with digital and analog architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features and to meet functional, performance, and power goals. The additional responsibilities include: development of validation strategies and plans, scoping and driving execution for different area of pre-Si validation, driving technical reviews of plans and proofs with design and architecture teams, maintaining and improving existing functional verification infrastructure and methodology, providing guidance and help to team members in understanding issues, removing roadblocks and ensuring issue resolution through strong demonstration of Intel Cultural values.

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