Experienced PCIe System Design Engineer

Responsibilities

• PCIe Design & Configuration: Defining and implementing PCIe Controller and PHY IP
• Protocol Logic Implementation: Implementing PCIe-specific features such as DOE, IDE, MFND/SR-IOV
• IP Integration & CSRs: Integrating PCIe/PHY IPs into the SoC fabric and defining/implementing the Control and Status Registers (CSRs) for hardware-firmware interaction
• Power & Reset Design: Designing power management mechanisms (ASPM, L1 Substates) and system-level reset sequences
• Silicon Bring-up: Performing PCIe link bring-up on silicon, testing connectivity, and optimizing the data path
• Advanced Debug: Troubleshooting multi-discipline complex issues using advanced AI debug tools and traditional equipment such protocol analyzers and oscilloscopes
• 7+ years of experience as a System/Design/Validation Engineer with a strong focus on PCIe
• Deep expertise in PCIe Gen 4/5 standards (Gen 6 is a major plus)
• Technical knowledge of NVMe protocol (Queue management, Admin/IO commands)
• Hands-on experience with PCIe protocol analyzers and high-speed oscilloscopes
• Proficient in Python/C for test automation and hardware debugging
• B.Sc. in Electrical Engineering or Computer Engineering from a leading academic institution
• Ability to work in a multidisciplinary configuration and collaborate with diverse teams

Additional Information

We are looking for a hands-on System Engineer, focused on the design, implementation, and silicon validation of PCIe interfaces within our SoC. The role requires a deep understanding of protocol layers, detailed design of the controller and its integration, and performing deep-level hardware debugging and silicon bring-up to ensure high-speed connectivity and NVMe compatibility.

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Company Intel

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