Principal RTL Design Engineer

Requirements

• To be successful in this role, you must:
• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field
• 12+ years of experience in digital IC or SoC RTL design
• Deep expertise in RTL using System Verilog design and micro-architecture
• Strong understanding of clocking, reset, and power-aware design, SoC architecture, processor cores, memory, peripheral interfaces through hand on prior experience
• Hands-on experience with lint, CDC, and RDC analysis
• Proven ownership and track record of block or subsystem delivery on production silicon with aggressive development schedules.
• Strong debugging and problem-solving skills and multi-tasking
• Hands on experience in scripting language such as Perl/Python.
• Familiarity with low-power design techniques
• Exposure to synthesis, STA, or physical design flows
• Experience mentoring engineers or leading technical reviews
• Expected Base Pay Range (USD)
• 160,400 - 237,320, $ per annum
• The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.
• Additional Compensation and Benefit Elements
• All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
• Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com .
• Interview Integrity
• To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription app

Benefits

Additional Information

About Marvell Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Marvell Custom Solutions partners with the world's most advanced technology companies-including leading hyperscalers, cloud data center operators, and telecom providers-to architect and deliver next-generation custom silicon that powers AI infrastructure, cloud computing, and 5G networks. Our team drives innovation at the forefront of semiconductor design, working on cutting-edge System-on-Chips (SoCs) built in the most advanced process nodes (3nm, 2nm) that leverage best-in-class IP portfolios spanning high-speed SerDes (112G+), advanced die-to-die interconnects, custom HBM memory architectures, PCIe Gen 6/7, and CXL 3.0 technologies-all integrated using breakthrough advanced packaging techniques including 2.5D, 3D, and co-packaged optics. In Custom Solutions, you'll collaborate with elite engineering teams across disciplines-from architecture and design through validation and production-to solve complex technical challenges that directly impact how billions of people experience technology, ensuring that every design meets the exacting specifications and performance requirements that our customers depend on to power their mission-critical infrastructure. What You Can Expect As a Principal Design Engineer, you will lead micro-architecture and RTL development and HW/SW co-design efforts working across multi-functional teams, in developing state-of-the-art designs. Own RTL design, implementation, and integration of complex blocks or subsystems Define and influence block-level and subsystem-level micro-architecture Develop high-quality, synthesizable RTL using Verilog/SystemVerilog Ensure design correctness through lint, CDC, RDC, and peer reviews Collaborate with verification, validation, Firmware and synthesis/STA, and physical design teams Identify and resolve complex functional, timing, power and integration issues Contribute to digital design methodologies and best practices Mentor and guide junior engineers Lead design and tape-out readiness reviews

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