Lead ASIC Design Verification Engineer (Starshield Satellite Engineering)

Responsibilities

• Lead a team responsible for digital ASIC verification at block and system level.
• Lead and execute verification test plan, development, and milestones from beginning to end, develop test harnesses and test sequences.
• Develop SystemVerilog testbench infrastructure (both UVM and non-UVM) for testing designs, including DSP blocks.
• Responsible for overseeing test plan execution, running regressions, code and functional coverage closure.
• Contribute to pre-silicon verification, chip bring-up and post-silicon validation.
• Work with leaders across the engineering organization to drive product requirements to push the performance envelope for Starshield satellites.
• Recruit, develop, train, and retain world class team members who will deliver for our Nation and amplify the team.

Requirements

• Bachelor's degree in electrical engineering, computer engineering, computer science, or another engineering discipline.
• 4+ years of experience with design verification and test bench development.
• PREFERRED SKILLS AND EXPERIENCE:
• Advanced degree in electrical engineering or computer engineering.
• Experience with verification methodologies such as UVM/OVM/VMM.
• Strong object-oriented programming knowledge.
• Strong problem-solving and coding skills.
• Experience in constrained random verification.
• Expertise in developing test plans, implementing coverage models, and analyzing results.
• Experience with scripting languages, e.g. Python for automation.
• RTL design, chip bring-up, and post-silicon validation experience.
• Ability to work in a dynamic environment with changing needs and requirements.
• Team-player, can-do attitude and ability to work well in a group environment while still contributing on an individual basis.
• Enjoy being challenged and learning new skills.
• ADDITIONAL REQUIREMENTS:
• Ability to work long hours and weekends as necessary to support critical milestones.
• Willingness to travel for off-site testing.
• An active clearance may provide the opportunity for you to work on sensitive SpaceX missions; if so, you will be subject to pre-employment drug and random drug and alcohol testing.
• COMPENSATION AND BENEFITS:
• Pay range:
• Lead: $160,000.00 - $225,000.00/per year
• ITAR REQUIREMENTS:
• SpaceX is an Equal Opportunity

Benefits

Additional Information

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. LEAD ASIC DESIGN VERIFICATION ENGINEER (STARSHIELD) Starshield leverages SpaceX's Starlink technology and launch capability to support national security efforts. While Starlink is designed for consumer and commercial use, Starshield is designed for government use, with an initial focus on earth observation, communications, and hosted payloads. The Lead ASIC Design Verification Engineer will lead a team that supports custom ASICs and FPGAs design for cutting edge satellites systems that deliver unprecedented quantities of data at unheard of speeds to the service-members who defend our Nation and Allies. From initial design through on-orbit operations this person is responsible for leading a phenomenal team of engineers in a collaborative effort to design, manufacture, test and operate chips for satellites that make our Nation safer.

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