ASIC Design Student

Responsibilities

• Assist in the development of micro-architecture, RTL coding, and debugging for complex digital blocks
• Utilize industry-leading EDA tools (Lint, CDC, Synthesis) to ensure designs are robust and power-efficient
• Work closely with the verification team to run simulations, analyze results, and ensure design quality
• Interact with Architecture and Backend teams to understand the full chip development lifecycle
• Help leverage AI-based automation tools to optimize engineering workflows

Requirements

• Pursuing a Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical field
• Strong academic record with a focus on Digital Logic Design and VLSI
• Ability to work at least 2 days per week at our Haifa/Tel Aviv center
• Solid understanding of logic design principles and hardware description languages (Verilog or SystemVerilog)
• A "can-do" attitude with a passion for solving complex technical challenges
• Fluent in Hebrew and English with the ability to work effectively in a team environment
• Hands-on experience with FPGA projects or university-level tape-out projects
• Proficiency in Python, Perl, or Bash for automation
• Completed courses in Computer Architecture, Synthesis, or Static Timing Analysis (STA)
• Basic familiarity with high-speed protocols like PCIe or DDR

Benefits

Additional Information

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary ASIC Design Student to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, designing c omplex solutions that sit at the heart of our most ambitious connectivity projects. As an ASIC Design Student, you won't just build chips-you will be part of a team defining the next generation of AI infrastructure main components. The complex digital blocks under your micro-architecture and implementation responsibilities will power the world's largest AI clusters. You will own the journey from high-level definition through RTL implementation and backend support, transforming complex logic challenges into elegant, high-performance hardware. If you thrive on solving unnamed challenges in deep-submicron processes and want to shape the digital design foundation for AI infrastructure connectivity, this is your opportunity.

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