Manager CAD Engineering (f/m/d)

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About Operations Engineering Division (OED): OED is the central team that supports all Business Unit Design and Development teams, and other organizations including Sales, Marketing, Business Operations, Foundry Operations, and Test. OED provides a platform for managing all process technology and PDK development for both Internal and External Foundry processes. This strong and highly qualified team (mostly MS/PhD) adds strength in developing Test Technology, Foundry Operations, and Yield management. Our world class contributions lead to aggressive NPI strategies and continual cost and gross margin improvement. The PDK team: Within OED, the PDK team works with internal and external foundries to develop and deploy high quality PDKs on both mature and advanced nodes. This global, dynamic and fast-paced team interfaces directly with foundries and EDA tool vendors, as well as internally through foundry tech teams, packaging teams and design and layout communities to provide highly integrated, state of the art PDKs and PDK flows/solutions. The PDK is a core and essential part of all our design flows from concept to tapeout for every project. The open position: The PDK team is looking for an experienced Staff PDK/CAD Physical Verification (PV) Engineer based out of EU region to enhance the team's support for our business units. The role includes leading a small team of PV engineers. Duties and Responsibilities Development : Define, drive & support PDK team in conceptualizing, planning, specifying, development, QA & documentation of company-wide Physical Verification methodology, flows. Development : Maintain, update, and improve internal QA system for PV components Development : Review, adapt, update, enhance and release foundry DRC/LVS/Parasitic Extraction/PERC/FILL rundecks for Renesas internal customers. Development : Conceptualize, develop, test, and deploy tools after identifying needs of internal customers and/or gaps in EDA tools Development : Be interface between design, foundry technology and assembly teams to identify and implement project requirements, find, and address different issues from PV side (decks, tools, technology) Development : Interface with EDA tool vendors to support Renesas tool evaluations and drive enhancements and bug fixes as needed. Development : Interface with foundries to drive high‑quality PDK deliverables, identify gaps and inconsistencies, and track, report, and ensure timely resolution of issues through to closure. Support : Provide support to Renesas internal customers (Analog Design teams & Digital P&R design teams) on DRC/LVS/FILL and Parasitic extraction, and internally developed tools. Support : Provide releases, QA and documentation for existing PV components to enable on-time Tape-Outs Support : Support Tape-Outs from Physical Verification side, e.g., help/debug of DRC/LVS/FILL and PEX issues/results to achieve Tape Out schedule Support : Work closely with design and layout teams to identify PV flow requirements or deficiencies and provide solutions for the same. Leadership : Understanding timelines, responsibilities, and priorities for the assigned projects, define and oversee same for the PV team members Leadership : Manage a team of internal PV engineers, setting priorities, goals and ensuring deliverables and support to projects are fully met. Deep understanding & knowledge of tools and programming language for DRC, LVS, FILL and Parasitic Extraction (SVRF/TVF and TCL) or PVS/Pegasus equivalents is a MUST Good knowledge of CMOS fundamentals with background in electrical engineering or semiconductor physics Knowledge of modern semiconductor technology and design flows Knowledge of foundry PDKs and their internal components: PCELL, CDF, Tech files. Strong debugging capability, not limited only by Physical verification flows. Knowledge/Understanding FILL methodology Knowledge/Understanding Parasitic effects in ICs (Integrated Circuits) Experience in Calibre PERC applications, e.g., P2P/CD is a plus Experience in any commercial flow for RDSON, EMIR is beneficial Experience in DRC/LVS/PEX/PDK QA and QA automation Tape-Outs support on demand Knowledge of UNIX shell, Shell scripting, makefiles & programming, excellent grasp of either Perl or Python. Additional, Desired Qualifications/Skills Master's degree in electrical engineering or equivalent degree with 10 years of experience. Familiarity on Cadence custom IC Virtuoso platform, Virtuoso-L and Virtuoso-XL, schematic capture, and layout concepts. Management experience is beneficial Renesas is an embedded semiconductor solution provider driven by its Purpose ' To Make Our Lives Easier .' As the industry's leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded P

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