Senior Optical Signal Integrity / Power Integrity (SI/PI) Engineer

Responsibilities

• Lead signal integrity (SI) and power integrity (PI) efforts for high-speed optical transceiver modules, high density optical interconnect platforms.
• Design and simulate high-speed channels up to 448G per lane (e.g., 224G/448G PAM4) across PCBs, packages, and connectors.
• Perform pre- and post-layout SI/PI simulations using tools like Ansys HFSS, Keysight ADS, Cadence Sigrity, and SiSoft QSI.
• Develop and validate PCB stackups, via structures, high-speed breakout regions, and connector transitions to meet compliance with IEEE, CEI, and MSA standards.
• Work closely with electrical, optical, and layout teams to define routing constraints, reference plane designs, and return path continuity for minimal signal degradation.
• Design and optimize PDNs to meet target impedance, minimize noise coupling, and support fast transient loads for high-speed DSPs and ICs.
• Provide SI/PI layout guidelines to PCB designers and review placement/routing for high-speed paths and power domains.
• Collaborate with validation teams to perform measurements (TDR, VNA, eye diagram, jitter, BER) and correlate with simulation models.
• Engage with ASIC, connector, and packaging vendors to support co-design and channel optimization across multiple integration layers.
• Drive root cause analysis of SI/PI-related issues during validation and production builds.
• B.S. or higher in Electrical Engineering, Applied Physics, or a related discipline.
• 7+ years of experience in SI/PI engineering for high-speed interconnects in optical or networking hardware.
• Proven experience with 112G, 224G, and 448G PAM4 signaling and related SI/PI challenges.
• Strong understanding of PCB stackup design, via modeling, impedance control, and crosstalk mitigation.
• Expertise in signal integrity simulation tools such as Ansys HFSS, Keysight ADS, Sigrity, or similar.
• Experience with power delivery design, including decoupling strategies, PDN impedance analysis, and noise mitigation techniques.
• Familiarity with transceiver MSA form factors (QSFP-DD, OSFP) and standards from IEEE, CEI, OIF.
• Hands-on experience using TDRs, VNAs, oscilloscopes, and other lab equipment to validate simulation results.
• Excellent problem-solving, documentation, and cross-functional communication skills.

Requirements

• M.S. or Ph.D. in Electrical Engineering or a related field with emphasis on high-speed or mixed-signal systems.
• Experience with co-packaged optics, chiplet-based architectures, or advanced substrate technologies.
• Familiarity with EMI/EMC considerations and signal/power isolation in densely integrated photonic-electronic systems.
• Understanding of thermal and mechanical effects on SI/PI performance and long-term reliability.
• Experience working with fabrication vendors, ASIC teams, and contract manufacturers to ensure end-to-end channel integrity.
• Compensation Information:
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Benefits

Additional Information

Who You'll Work With You'll work closely with hardware architects, ASIC vendors, layout, packaging, and optical teams to co-optimize performance, manufacturability, and reliability for state-of-the-art networking hardware.

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Company Intel

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