Principal Engineer - Design For Test (DFT)

Requirements

• Bachelor's, Master's degree or PhD in Computer Science, Electrical Engineering or related fields with minimum of 10 years of work experience.
• Direct DFT experience with at least 8 years in the custom chip (ASIC) design business
• Hands-on working experience in various stages of DFT-Execution: SCAN/MBIST/Validation/STA/IP-DFX/Post-Silicon Bring-up/Debug
• Thorough knowledge on various DFT/Test architecture solutions for 2.5D/3D IC design.
• Strong fundamentals in digital circuit design and logic design
• Understanding of DFT flows and methodologies and experience with Siemens/Synopsys Tool set (Tessent, Spyglass/Tmax, Genus, Modus, NCSim/DC), with Tessent the EDA tool flow in use.
• Proven track record of problem solving and innovation to meet challenging design requirements.
• Excellent team player and can work with different function leaders, across different geographies to define and execute the DFT project to completion.
• Excellent communications skills both verbal and written.
• Scripting skills using Python, PERL, Tcl and C-Shell is plus.
• Expected Base Pay Range (USD)
• 160,400 - 237,320, $ per annum
• The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.
• Additional Compensation and Benefit Elements
• All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
• Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com .
• Interview Integrity
• To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.
• These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in

Benefits

Additional Information

About Marvell Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact As a Digital IC Design Principal Engineer with Marvell, you'll be a member of the Custom Silicon Engineering team. This team is a leader in large multi-die designs that drive high compute performance and acceleration in many markets, including custom AI, 5G and 6G. The role will be challenging and will require an experienced DFT engineer that can work with existing DFT solutions while also creating new solutions to address industry first issues. What You Can Expect The position will be responsible for implementing DFT/Test on complex IP and SOC for multiple custom/compute ASIC/SoC designs. The work will involve running Tessent tools for insertion of all DFT structures. The role will involve chiplet DFT solutions, will include Tessent SSN, and will require strong verification and debug skills. The engineer will need to show proficiency in ICL/PDL, PTAP/STAP, 1687. It is a requirement that the engineer is knowledgeable in instrument-level access inside a chip. The engineer will work with other leads to help with Design-for-Test architecture definition and implementation of additional DFT/DFX features The engineer will also be involved in STA constraint definition, pattern generation & post-silicon bring-up and debug. In this position, the responsibility will grow to include mentoring, guiding and driving a small team of DFT engineers. The engineer will work with other leads to help enhance DFT methodologies and tools.

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