Senior Staff Physical Design Feasibility Engineer
External
Samsung · 3900 N Capital Of Texas Hwy, AustinPrepare for this interview
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Requirements
- 10+ years of experience with a Bachelor's degree in Computer Science/Computer Engineering/relevant technical field, or 8+ years of experience with a Master's degree, or 6+ years of experience with a PhD
- Proven track record of delivering high-quality designs that meet PPA goals and functionality requirements.
- Solid understanding of SOC/ASIC design flow utilizing the latest industry P&R tools.
- Experience in block-level floor-planning and PPA optimization.
- Knowledge of logical equivalence checking, timing constraints, and Verilog.
- Basic understanding of GPU architecture and data flow.
- Proficient scripting/programming skills in TCL, Perl, Shell, and/or Python.
- Knowledge of Electrical Engineering fundamentals, analytical aptitude, and excellent attention to detail.
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Benefits
Additional Information
Position Summary Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy - the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices (mobile, automotive, and other custom market segments) consumed by millions of people around the world. Come build with us! Role and Responsibilities As a Senior Staff Physical Design Feasibility Engineer, you will play a crucial role in driving the overall performance, power, and area (PPA) of complex ASIC and interposer designs, focusing on ensuring their feasibility and success from initial floor planning through to tape-out and sign-off. This senior-level position involves providing technical leadership, collaborating across teams, and optimizing and validating GPU design modifications to meet critical timing, power, area, and reliability targets, all of which present exciting technical challenges. You will engage with architects within the IP and at the SoC level to drive architectural definition and deliver quality micro-architectural level documentation. You will collaborate with RTL designers to evaluate PPA and drive improvement of new architectural features or RTL changes. You will be responsible for synthesis, floor planning, place & route in chip-level and hierarchical physical implementation environments. You will produce and deliver RTL/netlist to GDS flow, meeting PPA (Power, Performance, and Area) goals and ensuring proper functionality. You will utilize Perl, TCL, Shell, and other script languages to automate design flows and improve efficiency. You will apply your knowledge of GPU design and integration flows, including CPU/GPU/ASIC physical design experience, to drive innovation and excellence in our designs. You possess strong communication skills, are a team player who thrives in a collaborative work environment, and have discipline and planning abilities that enable you to execute with high-quality deliverables.
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