Post-Silicon Validation and Methodology Engineer

Responsibilities

• Own bring-up, validation, qualification, tuning, and productization plans for next-generation silicon - from first power-on through PVT sign-off.
• Partner across architecture, build, firmware, and software teams to define requirements for power management and clocking features, then drive coverage from pre-silicon through production.
• Build the test infrastructure, characterization methodologies, and bring-up playbooks that shift post-silicon coverage left and raise velocity across programs.
• Lead root-cause analysis on the hardest HW/SW interaction issues - with the measurement field, instrumentation judgment, and hypothesis rigor to close them under schedule pressure.
• Identify where current processes break and redesign them: bring-up sequencing, debug forums, regression frameworks, and the lab metrics that tell us whether we are actually improving.
• What we need to see:
• BS or MS in Electrical or Computer Engineering (or equivalent experience), plus 5+ years in silicon bring-up, validation, debug, or productization.
• Deep fundamentals across digital development, microarchitecture, timing, clocking, power, noise, and control systems - and the ability to reason across the HW/SW boundary under real lab constraints.
• Hands-on lab proficiency: oscilloscopes, logic analyzers, power analyzers, and the instinct to know which instrument answers which question during a bring-up.
• Strong programming and scripting proficiency: Python, C/C++; experience building lab automation or test infrastructure that other specialists adopt and depend on - not just personal scripts.
• Ways to stand out from the crowd:
• Hardware proof of crafting: debug infrastructure you built in the lab, characterization methodologies adopted across programs, build DFT feature specs or in-system test suites you developed, or margin test flows that caught issues before production.
• Proficiency in bring-up experience with GPU/SoC architecture
• Experience crafting or scaling in-system test and DFT features for production silicon, with familiarity with fault models, DPPM, and RAS.
• Build concrete examples of redesigning how a team debugs in the lab - faster triage, smarter hypothesis trees, automated measurement reporting - and the resulting increase in bring-up velocity or quality.
• Widely considered to be one of the technology world's most desirable employers, NVIDIA offers highly competitive salaries and a comprehensive benefits package. As you plan your future, see what we can offer to you and your family www.nvidiabenefits.com/
• #LI-Hybrid
• Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 136,000 USD - 218,500 USD. You will also be eligible for equi

Additional Information

Join NVIDIA, a trailblazer at the forefront of graphics and artificial intelligence performance, efficiency, and innovation. From our roots as a groundbreaking graphic company, we have evolved into a global leader in artificial intelligence, continuously pushing the boundaries to tackle complex challenges across diverse industries. The problems that break late in a silicon program almost always break here first - at the boundary where architecture, design, firmware, and silicon meet reality in the lab. NVIDIA's Silicon Co-Design Group has an end-to-end view that almost no team anywhere can claim: from early architecture through bring-up to product release, across GPU, SoC, and CPU programs spanning Datacenter, Gaming, Robotics, Automotive, and Embedded. We are looking for a hardware engineer who builds the methods, test infrastructure, and coverage strategies that find issues before software is production-ready - and who rewires the team's workflow when the old approach isn't fast enough.

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