ASIC Packaging Signal/Power Integrity Engineer (Hybrid)

Responsibilities

• We are seeking a qualified Signal and Power Integrity Engineer to help us develop our next generation ASIC packaging to help define, design and verify ASIC packaging to be deployed in a range of Cisco platforms.
• Develop, document, and implement design rules for ultra-high-speed signaling, ensuring power, performance, and area goals are met for products.
• Analyze substrate signal integrity (SI) and power integrity (PI), providing feedback and collaborating with the layout team to develop optimal solutions across interposer, substrate, and PCB.
• Design, document, and develop ASIC packages for high-volume, high-quality release, including post-layout extraction and reporting.
• Collaborate with system partners, vendors, and design leads to achieve combined power and signal integrity and to resolve complex technical issues using advanced technology design rules.

Requirements

• High-Speed Architecture & Theory: Expertise in high-speed design principles, including Transmission Line Theory, electromagnetics, scattering parameters, and impedance network analysis, applied to 56G PAM4 SerDes architectures, channel modeling, and BER prediction.
• SI/PI Simulation Proficiency: Experience with pre- and post-layout signal and power integrity (SI/PI) simulations using industry-standard EDA tools such as Cadence Sigrity, Ansys HFSS, and Keysight ADS.
• Layout Review & Physical Validation: Experience conducting detailed layout reviews and physical design validation using tools such as Cadence APD and Ansys EM flows to ensure signal performance and crosstalk mitigation.
• Circuit Analysis: Working knowledge of SPICE for circuit-level analysis, signal modeling, and performance validation.
• Skilled in articulating ideas and technical concepts to diverse audiences, both verbally and in writing.
• Experience with high-bandwidth memory (HBM) or high-speed memory interface SI.
• Experience with die-to-die interfaces (UCIe or proprietary).
• Experience with advanced packaging (CoWoS, EMIB, interposer-based designs), including SI/PI analysis of 2.5D ASIC packaging.
• Working knowledge of Vector Network Analysis.
• Basic knowledge of IBIS.
• Why Cisco?
• We are Cisco, and our power starts with you.
• Message to applicants applying to work in the U.S. and/or Canada:
• The starting salary range posted for this position is $152,500.00 to $219,200.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compe

Additional Information

The application window is expected to close on: 09/25/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received . This position requires that you live within commuting distance of our San Jose, CA office and commute to the office at least 4-5 days per week. Meet the Team Cisco Silicon One (#CiscoSiliconOne) is a business organization with a long track record of building complex and high-performance Silicon ASICs. Our silicon devices drive the world's most complex networks and carry over 90% of IP traffic. Cisco Silicon One is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. We are a highly specialized ASIC team with experts in all aspects of advanced IC package design and heterogeneous system integration. Our substrates use the latest 2.5D fanout technologies for large-scale integration, using the latest signaling and data transfer technologies. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed in the industry!

Your Match

How well this role fits your profile.

Company Intel

What employees say

Worked at Cisco? Share your experience