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ASIC Digital Verification Engineer

External
Renesaselectronics logoRenesaselectronics · Ottawa, CA
$76K–$100K/yrFull-timeOn-site2d ago
ComplianceIoTLinuxVerilog
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Responsibilities

  • Define and implement self-checking test cases based on functional requirements
  • Contribute to our ever-evolving verification infrastructure components
  • Triage of regressions, debug of RTL and Gate level simulations, analysis of coverage, and working with other teams to resolve issues and achieve verification closure
  • Work with diverse design and verification team members, local and remote
  • ENTRY LEVEL - Bachelor's degree with up to 2 years of experience or a recent master's grad with no experience.
  • Understanding standard specifications/ functional specifications/ feature enhancements for the product to create and execute detailed verification plans
  • Knowledge of SystemVerilog and UVM environments for digital verification
  • Experience with Synopsys and/or Cadence simulation tools
  • Experience with System Verilog assertions, functional coverage, and code coverage
  • Fast learner with the ability to work under minimal supervision
  • Effective team player with good communication skills
  • Ability to work in a Unix/Linux operating system environment
  • Are you ready to own your success and make your mark?
  • Join Renesas. Let's Shape the Future together.
  • Export Control Compliance Condition
  • Successful candidates must

Benefits

Vision insuranceRemote work optionsPerformance bonus

Additional Information

ENTRY LEVEL - Bachelor's degree with up to 2 years of experience or a recent master's grad with no experience. 100% onsite Our Ottawa office is looking for a talented ASIC Digital Verification Engineer to join our team. Our team is developing industry-leading mixed-signal Digital PLL Application specific integrated circuits. You can be a part of a growing mixed design and verification team giving you a chance to make a significant impact. You would not only be contributing to the actual testcase development but also be part of the verification planning and the continuous improvement of our verification environment using the latest methodologies.

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