Physical Design Manager

About the role

We are looking for a Physical Design Mananger who will operate in a hands‑on, execution‑first player‑coach role. This position combines direct technical contribution with first‑line people leadership. The ideal candidate is someone who wants to stay deeply involved in physical design and timing closure while guiding a small team through critical execution phases. This is not a pure people‑management role . Success in this position is measured by delivery, convergence, and technical ownership , not by team size. Technical Qualifications Bachelor's degree in Computer Science, Electrical Engineering or related fields and 10-15 years of related professional experience or Master's degree and/or PhD in Computer Science, Electrical Engineering or related fields with 5-10 years of experience or e quivalent professional experience in lieu of a formal degree Principal‑level physical design expertise with a proven track record delivering timing‑closed ASICs or complex SoCs Demonstrated success in timing analysis and closure across multiple designs Deep understanding of advanced timing concepts including SI, CDC, LVF, POCV , and related methodologies Strong proficiency with PD and STA tools (e.g., Synopsys PrimeTime or equivalent), scripting, and UNIX/Linux environments Strong written and verbal communication skills with the ability to articulate technical tradeoffs Leadership Experience (Execution‑Focused) Experience leading PD engineers in a first‑line, hands‑on capacity Proven ability to operate as a player‑coach , contributing technically while guiding others Experi

Requirements

• Principal Physical Design Manager (Player‑Coach, Hands‑On)

Benefits

Additional Information

About Marvell Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact About Marvell Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud, networking, and AI architectures, our innovative technology is enabling new possibilities-from high‑performance compute to intelligent data movement at scale. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful, enduring innovation-above and beyond fleeting trends-Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Built on decades of expertise and execution, Marvell's Custom Processor and ASIC Solutions organization delivers a differentiated approach through a best‑in‑class portfolio of data infrastructure intellectual property and flexible engagement models. Our custom silicon powers some of the most demanding workloads in the industry, spanning cloud data centers, networking, storage, and next‑generation AI platforms. In this role, you will contribute to both the physical design and methodology development for future generations of high‑performance processor and accelerator silicon, implemented in leading‑edge CMOS process technologies. These designs are directly targeted at AI training and inference, cloud compute, and high‑bandwidth networking applications, where power, performance, and scalability are critical. You will work at the intersection of advanced physical design, timing closure, and AI‑driven compute demands, helping to enable custom silicon solutions that accelerate innovation across the data infrastructure ecosystem. Work Location This role is onsite at Marvell's Westborough, Massachusetts location. Remote or Hybrid opportunities are not offered at this time. Relocation assistance will be provided for qualified candidates. What You Can Expect Job Responsibilities Serve as the primary technical owner for physical design and timing closure on assigned blocks, partitions, or subsystems Perform hands‑on physical design and timing analysis , including late‑stage debug and convergence Define and actively drive closure strategy , not just review results Act as a key technical escalation point , stepping in directly when progress stalls Lead and mentor a small team of PD engineers as a player‑coach Provide prioritization, technical direction, and day‑to‑day execution guidance Coordinate closely with STA, RTL, CAD, and Program teams to resolve complex issues Support hiring, onboarding, and ramp‑up of new team members while maintaining technical ownership Communicate execution status, risks, and tradeoffs clearly to engineering leadership

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Company Intel

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