Senior Engineer, Analog Layout

Requirements

• Bachelor's degree in Computer Science, Electrical Engineering or related fields and at least 5+ years of related professional experience or Master's degree in Computer Science, Electrical Engineering or related fields with 3+ professional experience.
• Deep understanding of layout methodology from initial chip planning to tape-out and parasitic optimizing in layout
• Experience in advanced process technology and Fin-FET is preferred
• Have a high level of proficiency in interpretation of CALIBRE DRC, ERC, LVS, etc. reports
• Possess high-level proficiency/knowledge of Synopsys or CADENCE layout entry tools
• Programming skills in any of the following are a plus: Skill or Ample or Perl, etc.
• Strong technical and analytical background, problem solving skills, etc.
• The candidate must have a proven record of laying out high-performance analog circuits in state-of-the-art CMOS process technologies, successfully performed top-level integrations, and placed products into volume production multiple times.
• Proficient in spoken and written English
• Job Responsibilities
• Regular meetings with your paired designer ensure collaborative information sharing, integral to Marvell's commitment to partnership and teamwork.
• Key contributor and crucial role in the project lifecycle, participating in routine meetings as a technical mentor, layout team, and the broader project team.
• Provide updates on progress and may involve presenting specific issues or solutions encountered during the development of cutting-edge technologies
• Continuous learning and knowledge-sharing among colleagues

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Company Intel

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