Senior ASIC Synthesis and STA Engineer

Requirements

• Experience with additional front end or back end design activities such as floorplanning , Design for Testability (DFT), or place and route
• Hands on exposure to deep submicron ASIC technologies and advanced timing closure methodologies
• Scripting experience (e.g., Python, Tcl , or similar) to enhance automation and debug workflows
• Background supporting DSP centric or high speed ASIC development programs
• Experience working with external EDA vendors or foundry technology teams
• Pay Range:
• The annual salary range for this position is $109,000 - $174,000 CAD.
• At Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard. Ciena values the diversity of its workforce and respects its employees as individuals. We do not tolerate any form of discrimination.
• Ciena is an Equal Opportunity Employer, including disability and protected veteran status.
• If contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require.

Benefits

Additional Information

As the global leader in high-speed connectivity, Ciena is committed to a people-first approach. Our teams enjoy a culture focused on prioritizing a flexible work environment that empowers individual growth, well-being, and belonging. We're a technology company that leads with our humanity-driving our business priorities alongside meaningful social, community, and societal impact. Ciena's next-generation Wavelogic Digital Signal Processor (DSP) programs rely on deep technical excellence, cross-functional collaboration, and continuous innovation. This role offers the opportunity to shape the front end implementation of industry leading ASIC technology and contribute to the methodologies that keep Ciena at the forefront of high performance optical networking. How you will make an impact: Execute front end implementation for assigned IP subsystems, including synthesis, static timing analysis, logical equivalence checking, and clock domain crossing validation Develop and maintain timing constraints to support synthesis and signoff for subsystem integration Perform logical equivalence verification between Register Transfer Level (RTL) and gate level netlists throughout pre and post layout stages Validate clock domain crossings for top level ASIC integration to ensure functional integrity Create and optimize scripts, tools, and documentation that improve synthesis and static timing workflows Implement engineering change orders (ECOs) to support iterative design refinement Collaborate closely with ASIC integration, IP development, physical design, and external Electronic Design Automation (EDA) partners to align front end and back end implementation activities The must haves: B.Sc. in Electrical Engineering, Computer Engineering, or a related discipline (or equivalent experience) Industry experience using synthesis and/or static timing analysis tools within an ASIC development environment Knowledge of ASIC implementation flows, including synthesis, timing analysis, logical equivalence checking, and clock domain crossing validation Familiarity with RTL design principles and hardware description languages Ability to work effectively within multi disciplinary engineering teams and manage deliverables to project schedules

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