EDA Design Flow Development Engineer

External

Intel · California, Santa Clara

Full-timeHybrid1w ago

AssemblyCADComplianceLeadershipLinux

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Requirements

Bachelor's degree in Computer Engineering, Electrical Engineering, Computer Science, or a related field, and 6+ years of experience; 4+ years of experience with a Master's degree; or 2+ years of experience with a PhD.
EM/IR reliability concepts ( Electromigration, and Power Drop)
Experience with Redhawk/Totem tools
Experience in the following:
CMOS circuit operation
Power delivery networks
SPICE simulation
Parasitic extraction fundamentals
Advanced-node design challenges
Transistor-level power integrity analysis flows
Scripting and automation skills in Linux environments
Job Type:
Experienced Hire
Shift:
Shift 1 (United States of America)
Primary Location:
US, California, Santa Clara
Additional Locations:
US, California, Folsom, US, Oregon, Hillsboro, US, Texas, Austin
Business group:
Posting Statement:
Position of Trust
N/A

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel .Annual Salary Range for jobs which could be performed in the US: $141,910.00-269,100.00 USDWork Model for this RoleThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*Health insurancePaid time offEquity / stock optionsPerformance bonus

Additional Information

Job Details: Job Description: The Role and Impact Join Intel in shaping the future of technology. As an EDA Tools Hardware Engineer, you will play a pivotal role in enabling groundbreaking innovations that power Intel's leadership in semiconductor design and manufacturing. We are seeking an experienced EDA CAD / Tool Flow Development Engineer to develop and maintain transistor-level electromigration (EM) and IR drop analysis flows for custom IPs, embedded memories, SRAMs, analog/mixed-signal interfaces, and high-performance custom macros across advanced semiconductor technologies. This role focuses on CAD methodology, automation infrastructure, power integrity analysis flows, and silicon correlation for transistor-level reliability verification. The engineer will work closely with circuit design, physical design, package, reliability, and signoff teams to enable scalable and accurate EM/IR analysis methodologies for advanced-node designs. The ideal candidate has strong expertise in transistor-level power integrity analysis, SPICE-based verification, parasitic-aware reliability modeling, and automation development using industry-standard EM/IR signoff tools.

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