Mixed Signal Digital Design Lead

Requirements

• Bachelors and 8+ years of related experience
• Additional Job Description:
• Compensation and Benefits
• The annual base salary range for this position is $108,000 - $172,800 .
• If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

Benefits

Additional Information

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: Senior Mixed-Signal Lead to spearhead the architecture and design of high-performance clocking solutions, including PLLs, FLLs, and DLLs, for our next-generation silicon. In this leadership role, you will be responsible for the full lifecycle of analog timing IPs and post-silicon validation. The ideal candidate has 8+ years of experience in mixed-signal design with a specific focus on low-jitter, low-power frequency synthesis in advanced process nodes (N5, N3P). You will drive the trade-offs between analog and digital implementations of clocking circuits, ensuring seamless integration into large-scale SoCs. As a technical lead, you will manage external IP vendors, define internal design methodologies, and collaborate closely with Analog Design and Physical Design teams to mitigate noise coupling and power supply integrity issues. A deep understanding of jitter decomposition, phase noise analysis, and silicon bring-up is essential and Matlab, Arcsim experience is desired.

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Company Intel

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