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Senior/Staff Lithography Process Engineer

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STATS CHIPPAC MANAGEMENT PTE. LTD. logoStats Chippac Management · Yishun Industrial Park A, Singapore
S$72K–S$96K/yrFull-timeUnknownToday
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Responsibilities

  • Own and optimize lithography processes for PI, PR, and other patterning layers in both FO and FI eWLB.
  • Manage photolithography tools (GHI/i-line stepper, coat/develop tracks, etc.), including recipe setup and troubleshooting.
  • Lead cross-functional projects focused on cost reduction, process robustness, and NPI transfer.
  • Lead process improvements to enhance yield, throughput, and cost efficiency.
  • Evaluate and implement new lithography materials (PSPI, PR) and tools.
  • Define and maintain process documentation (SOP, OCAP, FMEA, SPC) and training programs.
  • Collaborate with equipment vendors, materials suppliers, and internal engineering teams to evaluate and qualify new tools or materials.
  • Design and perform DOE, root cause analysis, and statistical data analysis (e.g., JMP, Camline, etc.).
  • Support daily fab operations with issue resolution and yield improvement initiatives.
  • Mentor junior engineers and provide technical direction to the litho team.

Requirements

  • Bachelor's or Master's degree in Engineering (Materials, Chemical, EE, or related field).
  • 5+ years hands-on experience in photolithography process, preferably in advanced packaging (eWLB, WLP, FO-PLP).
  • Strong knowledge of lithography tooling, including exposure systems and coater/developer tracks.
  • Skilled in project management, process transfer, and cost/yield improvement.
  • Familiar with SPC, FMEA, and problem-solving methodologies.
  • Excellent communication skills, with proven ability to engage with both internal stakeholders and external customers.
  • Fluent in both English and Chinese. (This role will need to liaise with customers and counterpart from China)

Additional Information

As a Senior/Staff LithographyProcess Engineer, you will lead the development and optimization of lithographyprocesses for both Fan-In and Fan-Out eWLB (Embedded Wafer Level Ball GridArray) packaging technologies. You will be responsible for driving keyengineering projects such as yield improvement, cost reduction, and processtransfers across global manufacturing sites.


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