ASIC Physical Design Engineer
ExternalPrepare for this interview
EliteAI-generated questions, company research, and talking points tailored to this role
Responsibilities
- You will be responsible for macro level RTL to GDS implementation and signoff.
- Work with Front-End teams to understand the design architecture to ensure optimal physical implementation.
- Execute physical design tasks, including gate-level netlist synthesis, floorplanning, placement, Clock Tree Synthesis (CTS), and routing.
- Optimize designs to achieve industry-leading power, performance, and area (PPA) metrics while maintaining design integrity through formal verification.
- Conduct Static Timing Analysis (STA), physical verification, formal verification and signoff closure to ensure high-quality results.
- Analyze and resolve Electromigration (EM) and IR-drop (IR) issues, meeting stringent signoff requirements for reliability and performance.
Requirements
- Bachelor's or Master's degree in Electrical Engineering, Computer Science, or a related field.
- Minimum of 3 years of experience in ASIC design and verification
- Knowledge of block-level synthesis, place-and-route (PnR), and timing closure.
- First-hand experience with industry-standard PnR and signoff tools such as Synopsys and Cadence.
- Understanding of all aspects of physical design construction, integration, and methodologies.
- Proficiency in Physical Design Verification, including techniques like LVS and DRC.
- Experience with physical design EDA tools and workflows.
- Expertise in Static Timing Analysis (STA), timing closure, and design constraints.
- Proficiency in scripting languages like Tcl, Python, or Perl, with a focus on automation and efficiency improvements.
- Why Cisco?
- We are Cisco, and our power starts with you.
Additional Information
Meet the Team Step into Cisco's ASIC Physical Design Team, where innovation meets collaboration. As a group of highly skilled engineers, we're redefining what's possible in silicon technology. Our mission is to drive the future of chip design, managing full chip physical implementation from RTL to GDSII and beyond. Working hand-in-hand with Front-End teams, we transform cutting-edge designs into industry-leading silicon solutions. Here, you'll have the opportunity to shape tomorrow's technology, driving advancements in power, performance, and reliability with every project. Together, we're building the foundation for the future of connectivity.
Your Match
How well this role fits your profile.
Company Intel
What employees say
Worked at Cisco? Share your experience