Principal Engineer, ASIC Development Engineering (Physical Design, PNR, floor plan) 8 to 12 years of experience

Responsibilities

• Own subsystem/block-level floorplanning and end-to-end place-and-route (PnR) flow for low-power, high-performance designs, including debugging of timing, power, and area issues, clock tree analysis, and contributing to full-chip timing convergence and closure.
• Collaborate closely with cross-functional teams, including Design and DFT, to streamline and enhance the PnR flow.
• Drive robust IP integration strategies to ensure high-quality ASIC delivery while minimizing schedule risks.
• Perform in-depth design and timing analysis to identify critical paths and implement effective strategies to mitigate timing violations and improve overall design convergence.
• Stay current with industry trends and emerging technologies in PnR and related domains, and incorporate best practices into team workflows.
• Prepare and present comprehensive technical analyses, reports, and documentation to stakeholders.
• Promote a culture of innovation, collaboration, and continuous improvement within the PnR team.
• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related discipline.
• Minimum of 8 years of experience in the Place and Route (PnR) domain.
• Demonstrated track record of successful PnR execution across projects.
• Strong expertise in industry-standard PnR tools and methodologies (e.g., Synopsys Fusion Compiler, Cadence Innovus).
• Solid understanding of digital design fundamentals, physical design concepts, and semiconductor fabrication processes.
• Strong analytical and problem-solving capabilities, with a strategic mindset.
• Excellent communication and interpersonal skills, with the ability to collaborate effectively across cross-functional teams and stakeholders.
• Proven ability to prioritize tasks and manage multiple projects concurrently.
• Proactive, results-driven mindset with a strong focus on innovation and continuous improvement.

Benefits

Additional Information

Position Overview: We are seeking a highly skilled and experienced Principal Engineer for our PNR function. The successful candidate will be part to a team of talented engineers responsible for ensuring the PNR convergence of our complex semiconductor designs. This role requires a deep understanding of PNR methodologies, leadership skills, and a strategic vision to drive continuous improvement in our PNR processes.

Your Match

How well this role fits your profile.

Company Intel

What employees say

Worked at Sandisk? Share your experience