Sr. SoC Power Engineer, Annapurna Labs - Cloud Scale Machine Learning

Requirements

• Bachelor's degree in Computer Science, Computer Engineering, Electrical Engineering, or related fields
• BS + 6yrs or MS + 5yrs or PhD + 3yr in EE/CS
• Expert on power analysis tools like PrimePower, PowerArtist or similar
• Deep, circuit-level understanding of chip power
• Ability to give feedback to RTL designers and Physical Designers on how to reduce power
• Highly proficient with scripting language (Tcl, Perl, Python or similar)
• Good understanding of Physical Design, EM/IR, Power Integrity, and Thermal at the die, package, board, and server level
• Some experience with lab equipment and capable of doing lab power analysis
• Master's degree in Computer Science, Computer Engineering, or Electrical Engineering
• Familiarity with Make or similar for automation of power rollups
• Experience with RTL design (System verilog)
• Familiarity with EMIR analysis tools (Redhawk / Voltus)
• Experience with Zebu Emulator platform
• Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status.
• USA, CA, Cupertino - 183,000.00 - 247,600.00 USD annually

Additional Information

Our Machine Learning Acceleration (MLA) team develops the Inferentia and Trainium SoCs that are used to power today's AI workloads in datacenters all around the world. As a Sr. SoC Power Engineer, you'll contribute to the project at the ground level by modeling and estimating power at every stage of the design from early RTL to final netlist and by driving ways to reduce power consumption of our machine learning accelerators. We're searching for an experienced SoC Power engineer with a background in Power analysis with a proven track record of handling challenges at scale. In this role, you'll be working directly with architects, designers, verification engineers, software teams, and Physical Design experts - defining best practices to reduce power and model power consumption with high accuracy. Key job responsibilities * Responsible for full chip power analysis & modelling at various stages of design (RTL to gate level netlist) * Develop and maintain dashboards for power rollups * Work with designers, architects, Verification engineers and Physical Design engineers to develop vectors for IR analysis, Thermal analysis and power estimation * Give feedback to designers and architects on how to reduce power * Make power measurements in the lab and correlate back to simulations. * Work with Emulation engineers to model chip-level power consumption

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