ASIC DFT Technical Lead

Responsibilities

• Responsible for development of the comprehensive Design-for-Test (DFT) & DFx solutions and architectures that support ATE screening, in-system test, debug and diagnostics needs of the design.
• Lead the RTL implementation from the architecture specifications and required RTL quality checks implementations.
• Work with the team on Innovative Hardware DFT & test strategy aspects for new silicon device models, bare die & stacked die, driving re-usable test and debug methodologies and standards.
• Work with the team on DFT challenge identification, cross-functional solution brainstorming and implementation plan development, and lead a team of engineers to deliver expected implementations on schedule.

Requirements

• Bachelor's or a Master's Degree in Electrical or Computer Engineering required with at least 10+ years of ASIC Hardware Development experience.
• Prior experience on hardware design specifications and verification plan/matrix, RTL & testbench implementations.
• Prior experience on Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan.
• Post-silicon test bring up and debug experience; Ability to analyze and root cause test failures on silicon.
• Prior experience on RTL QA checks, including lint & CDC
• Scripting skills: Tcl, Python/Perl.
• Why Cisco?
• We are Cisco, and our power starts with you.
• Message to applicants applying to work in the U.S. and/or Canada:
• The starting salary range posted for this position is $210,600.00 to $305,100.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.
• U.S. employees are eligible for paid time away as described below, subject to Cisco's policies:
• 10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees
• 1 paid day off for employee's birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco
• Non-exempt employees** receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees
• Exempt employees participate in Cisco's flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (subject to availability and some business limitations)
• 80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar

Benefits

Additional Information

The application window is expected to close on: 07/03/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received . Meet the Team: You will be part of the Silicon One development organization as an ASIC implementation engineer in San Jose, CA. As a member of this team you will be involved in crafting cutting edge next generation networking chips.

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