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FPGA Silicon Design Verification Engineer

External
altera logoAltera · Bengaluru, India
Full-timeOn-site2w ago
LeadershipPerlPython
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Requirements

  • You must possess the minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
  • Bachelor's Degree in Electrical Engineer, Computer Engineering, or related field.
  • Minimum of 5Y of experience in the following:
  • Experience with SystemVerilog.
  • Experience with UVM or OVM methodology.
  • Experience with scripting perl/Python
  • Master's Degree in Electrical Engineer, Computer Engineering, or related field.
  • Experience with using C/C++ models as golden models to compare with RTL.
  • Experience with code coverage.
  • Experience with functional coverage.
  • Experience with X-propagation.
  • Experience with multiple RTL simulators.
  • Experience with regression testing.
  • Experience creating components that are reusable from block to top.
  • Experience in Ethernet/PCIE/AXI/DDR protocols is an added advantage.
  • Job Type:
  • Regular
  • Shift:
  • Shift 1 (India)
  • Primary Location:
  • Bengaluru, Karnataka, India
  • Additional Locations:
  • Posting Statement:

Additional Information

Job Details: Job Description: Altera, an Intel Company, provides leadership programmable solutions that are easy-to-use and deploy in applications from the cloud to the edge, offering limitless AI possibilities. Our end-to-end broad portfolio of products including FPGAs, CPLDs, Intellectual Property, development tools, System on Modules, SmartNICs and IPUs provide the flexibility to accelerate innovation. As a verification engineer you will work closely with design teams to architect effective and efficient testbench and verification strategies to promote effective debug and failure detection; build UVM infrastructure including monitors, drivers, and scoreboards; produce functional coverage and code coverage; monitor dashboards and regressions; analyze root cause; develop constrained random stimulus and shape content to effectively stress the design space; and create test plans to ensure functional correctness.


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