Analog Design Engineer, Principal

Requirements

• Proven experience in independently designing ICs, from architecture definition to lab characterization, with full macro/IP ownership.
• Solid proficiency in analog design, preferably in the multi-GHz range.
• Extensive experience in performing or supervising analog custom layout.
• Strong familiarity with EDA CAD tools.
• Expertise in IC performance measurement and debugging designs to correlate simulations with real measurements.
• Direct project experience in at least one of the following is a plus: Multi-Gbps electrical SerDes or electro-optical transceivers OR advanced CMOS nodes, including FinFET technologies.
• Strong communication, presentation, and documentation skills.
• Proficiency in both spoken and written Italian and English (minimum B2 level).
• We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.
• This role is a full-time, onsite position, requiring employees to work from the office five days per week . Candidates should be comfortable with an in-office work environment.
• This role is based onsite, five days per week . Please apply only if you are able to meet this requirement
• Expected Base Pay Range
• 64,500 - 86,000, EUR per annum
• The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.
• Additional Compensation and Benefit Elements
• All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
• Interview Integrity
• To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or a

Additional Information

About Marvell Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact The Central Engineering - Optical PHY (CE-OPHY) team designs high-speed and optical transceivers for communication infrastructure in long-haul, metro, and datacenter. We address the bandwidth, capacity, and power issues faced by cloud computing, mega data centers that power the social media giant platforms. Our innovative approaches have resulted in the company's products being first to market in many of the key areas, developing the most advanced chips and subsystem solutions to address the ever-increasing demand for higher data rates driven by video-on-demand, gaming, and other real-time data streams. We are seeking talented individuals to work on solving technical challenges with the most outstanding group of collaborators in the industry. Join our team of experts and make a difference in an exciting career opportunity. As a member of a dynamic CE-OPHY team, the candidate will be responsible for designing circuits used for high-speed optical transceivers. The member will have an opportunity to work on a deep submicron process and collaborate with the team on next-gen high-speed optical transceivers. What You Can Expect Analyze block specifications and select appropriate topologies. Design analog blocks at the transistor level. Supervise layout activities, provide guidelines, and conduct post-layout verifications. Model blocks and validate models. Collaborate with other teams to enhance existing solutions. Take responsibility for designing entire analog macros or IPs. Participate in cross-functional meetings and interact with other functions. Train and mentor junior designers. Location : Pavia, Italy. Work Model : Full-time, on-site.

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