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Graduate Talent (ISCP SoC Front End Team)

External
Intel logoIntel · Penang, Malaysia
ContractHybridToday
ComplianceVerilog
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Requirements

  • Bachelor/Masters Degree in Electrical and Electronics or Computer System or relevant fields with good CGPA.
  • Knowledge of digital design fundamentals and Object Oriented Programming is a plus.
  • Job Type:
  • Intel Contract Employee
  • Shift:
  • Shift 1 (Malaysia)
  • Primary Location:
  • Malaysia, Penang
  • Additional Locations:
  • Business group:
  • Posting Statement:
  • Position of Trust
  • N/A
  • Work Model for this Role
  • This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
  • *

Benefits

Equity / stock options

Additional Information

Job Details: Job Description: In this position, you will be involved in the training, design and development of next generation System-on-a-Chip which creates great user experience that goes into every Client system. Seize the opportunity to be part of a Design and Development team who are always seeking new challenge to push the frontiers of technology on Chipset and SoC IP for the latest Intel product. Within the team, you will be at the forefront of performing SoC Front End related activities ranging from IP integration to SOC verification using state of the art tools and methodology. We are looking for aspiring talents who will help us push the user experience to the next level that is only bounded by your imagination. As SoC GT, a typical cool day comprises of any of the following:- Learning of IP interoperability (in System Verilog, Verilog or other Hardware description language). Creative problem solving along the process of integrating an IP into SOC. Developing new scenarios to verify the functionally of IP in SOC. This includes documenting a test plan, coding test content or coverage points to validate the functionality of new architectural features of next generation designs. Developing efficiency capabilities for pre-silicon verification or integration methodology.


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