FPGA Development Tools Engineer - Synthesis

Responsibilities

• Synthesis Development:
• Design, implement, and optimize synthesis algorithms to convert RTL (Verilog/SystemVerilog/VHDL) into efficient gate-level representations.
• Compiler Toolchain Contribution:
• Contribute to the FPGA compiler flow, integrating synthesis with placement, routing, and timing (STA) stages.
• Optimization & QoR:
• Improve quality of results (QoR) by optimizing performance, power, and area through synthesis-driven techniques.
• RTL Analysis:
• Develop tools and methodologies for analyzing and transforming complex RTL designs.
• Cross-Functional Collaboration:
• Work closely with architecture, STA, placement, routing, and validation teams to ensure alignment across the toolchain.
• Debug & Validation:
• Analyze synthesis results, debug issues (timing, logic structure, mapping), and drive resolution.
• Tooling & Automation:
• Develop internal tools, scripting, and automation to improve synthesis flows and productivity.
• The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings , etc. We also offer incentive opportunities that reward employees based on individual and company performance.
• $ 149.1K - $ 215.9K USD
• We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations .

Requirements

• Required Qualifications
• 6+ years of experience in FPGA/ASIC design, EDA tools, or related fields
• RTL Expertise:
• Strong hands-on experience with:
• Verilog/SystemVerilog or VHDL
• RTL design and synthesis flows
• Technical Skills:
• Proficiency in C/C++ for tool development
• Strong understanding of algorithms and data structures
• Familiarity with debugging and performance analysis
• EDA / CAD Knowledge:
• Understanding of:
• Logic synthesis and optimization techniques
• FPGA or ASIC design flows (synthesis → P&R → STA)
• Timing-driven design considerations
• Problem Solving:
• Ability to analyze complex systems and develop scalable, high-performance solutions.
• Education:
• Experience with synthesis tools or FPGA toolchains (e.g., Quartus, Vivado )
• Knowledge of FPGA architectures (LUTs, DSPs, BRAM, interconnect)
• Familiarity with advanced optimizations (e.g., retiming, logic restructuring, resource sharing)
• Scripting experience (e.g., Python, Tcl )
• Background in compiler development or EDA algorithms
• Experience working in large, distributed engineering teams
• Why Join Altera
• Build core synthesis technology for next-generation FPGA platforms
• Influence compiler architecture and performance at scale
• Collaborate with world-class engineers across silicon, architecture, and software
• Job Type:
• Regular
• Shift:
• Shift 1 (United States of America)
• Primary Location:
• San Jose, California, United States
• Additional Locations:
• Posting Statement:

Additional Information

Job Details: Job Description: Altera is a leader in FPGA innovation, delivering programmable solutions that power AI, cloud computing, networking, and edge applications. Our FPGA compiler and development tools are central to enabling customers to efficiently design, optimize, and deploy complex hardware systems on advanced FPGA platforms. Position Overview Altera is seeking a FPGA Development Tools Engineer to join our Synthesis team , focused on advancing the next generation of FPGA compilation technology. In this role, you will develop and enhance synthesis capabilities that transform RTL designs into optimized hardware implementations, directly impacting performance, power, and area (PPA). The ideal candidate brings strong expertise in RTL design and synthesis, combined with a solid software engineering background and a passion for building scalable, high-performance EDA tools.

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