Layout Engineer (Semiconductor - Pasir Ris)

Responsibilities

• Develop, maintain, and optimize complex parameterized cells (PCells) for large-scale layout generation.
• Prepare device tape-out deliverables and coordinate with foundry design kits (FDK).
• Conduct device test structure data collection and analysis to support development activities.

Requirements

• Degree in Physics, Electrical Engineering, or related disciplines is preferred.
• 3 - 10 years of hands-on experience in custom layout design.
• Proficiency in layout tools such as Laker or Cadence Virtuoso.
• Strong programming skills in SKILL/SKILL++, Tcl, C/C++, or similar scripting languages for EDA environments.
• Proven ability to develop, debug, and support complex PCells and batch layout generation.
• Solid understanding of CMOS processes, device structures, and layout design rules.
• Good communication and teamwork skills.
• Self-motivated with a strong willingness to learn.
• Proficiency in English for liaising with English-speaking clients and stakeholders.
• We regret that only shortlisted candidates will be notified. However, rest assured that all applications will be updated to our resume bank for future opportunities.
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• EA Personnel Name: Zoe Lang Zhen Zhen
• EA Personnel Registration Number: R23117353
• EA License No.: 07C5771

Additional Information

[Job ID: 1641907] Job Summary: Join a dynamic semiconductor team to design advanced test structures and develop scalable layout solutions using cutting-edge tools.

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Company Intel

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