Memory Layout Staff Engineer

Requirements

• Education: BE/B.Tech or MS/M.Tech in Electrical/Electronics Engineering, Microelectronics, or related fields; 5+ years of hands-on SRAM compiler layout experience
• Strong understanding of semiconductor process technologies, device physics, and layout effects in advanced nodes.
• Full-custom memory layout development for SRAM compiler blocks
• Complete physical verification across EM, IR, LVS, DRC and related flows
• Work closely with circuit, architecture, and verification teams
• Drive layout quality, constraints, and design-rule adherence
• Support optimization, debug, and design-rule closure
• Proficiency with Cadence Virtuoso and industry-standard EDA tools; scripting skills (Perl, Tcl, SKILL) for automation are a plus.
• Excellent communication skills to collaborate with global teams and provide clear status updates.
• Self-motivated, adaptable, and eager to learn in a dynamic environment.
• Additional Compensation and Benefit Elements
• All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
• Interview Integrity
• To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

Additional Information

About Marvell Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Marvell's Central Engineering (CE) team drives the development of advanced SoCs across a wide range of end markets, leveraging cutting-edge process technologies, analog mixed-signal design, and advanced packaging. Within CE, the AMS (Analog Mixed Signal) team is responsible for the layout design of high-speed SerDes IPs and other complex analog circuits, playing a key role in enabling Marvell's next-generation semiconductor solutions. This role is critical in ensuring high-performance analog circuits are accurately and efficiently implemented on silicon. As technology nodes advance, analog layout faces increasing challenges in complexity and variability-demanding innovative design approaches and sophisticated tooling. Marvell offers the ideal environment to explore these challenges, providing both breadth across engineering domains and depth within your specialization. You'll be part of a small, agile team making a big impact across Marvell's product portfolio, including AI, cloud data center, storage, security, and networking. What You Can Expect Play a leading role in developing full-custom memory layout and sign-off verification flows Collaborate with circuit designers globally to translate schematics into efficient, high-performance layouts and drive end-to-end ownership from floor planning to tape-out. Ensure physical verification closure by resolving DRC, LVS, ERC, and antenna violations; perform EMIR analysis and implement fixes for IR drop and electromigration. Lead layout reviews, mentor junior engineers, and promote best practices, optimization techniques, and design rule compliance while fostering knowledge-sharing and process improvements. Stay ahead of evolving technologies and tools, and develop automation scripts (Perl, Tcl, SKILL) to enhance productivity and consistency.

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