SI/PI Intern
External
Etched · San JosePrepare for this interview
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Responsibilities
- Signal Integrity Analysis
- Build and validate 3D electromagnetic models using Ansys HFSS.Develop board and package channel models from ECAD design databases.Correlate simulation results with measurements and lab data.Support mixed package-board channel simulations and optimization.Design Collaboration
- Partner with PCB layout, package, hardware, and ASIC teams to improve signal integrity.Identify root causes of channel degradation and propose design improvements.Contribute to SI design guidelines and best practices.Representative Projects
- Program details
- 12-week paid internship
- Generous housing support for those relocating
- Daily lunch and dinner in our office
- Based at our office in San Jose, CA
- Direct mentorship from industry leaders and world-class engineers
- Opportunity to work on one of the most important problems of our time
- For any questions, contact internships@etched.com.
- How we're different
- We are a fully in-person team in West San Jose, and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.
Additional Information
About Etched Etched is building the world's first AI inference system purpose-built for transformers - delivering over 10x higher performance and dramatically lower cost and latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history. Job Summary As a Signal Integrity / Power Integrity Intern, you will help design and validate the next generation of high-performance AI systems. You will work closely with package, PCB, ASIC, and system engineers to analyze high-speed interfaces, extract channel models, and improve signal quality across our accelerator platforms. This role provides hands-on experience with industry-leading tools and real-world challenges involving PCIe, Ethernet, high-speed SerDes channels, advanced packaging, and multi-board systems.
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