RTL Design Engineer (ASIC/SOC)

Responsibilities

• Lead RTL design, simulation, and verification for company ASIC/SoC products, ensuring robustness.
• Integrate and validate IP blocks for seamless system functionality.
• Analyze requirements for Power, Performance, and Area (PPA), optimizing design trade-offs.
• Collaborate with backend team in RTL coding, implementation, and synthesis for successful tapeout.
• Create and maintain reusable IPs for AI/in-memory computing.
• Support Post-Si testing to ensure product functionality and quality.
• Mentor junior engineers to facilitate their professional growth.
• Contribute to design reviews for improved product performance and reliability.
• Stay current on RTL design methodologies for efficiency and quality.
• Collaborate with cross-functional teams for successful product development.

Requirements

• Minimum Master in Electrical Engineering with 5 years of working experience with emphasis on RTL/SoC/digital design .
• Proficient in Verilog and SystemVerilog.
• Proficient in VCS, Verdi, or similar industry-standard tools.
• Skilled in pre-layout and post-layout simulation.
• Knowledgeable about the design flow and collaboration with backend teams.
• Familiar with AMBA APB and AXI protocols.
• Familiar with RISC/Arm or other core architectures.
• __________________________________________________________
• HOW TO APPLY :
• Interested candidates, please submit your resume by clicking on "Quick Apply" or contact win@hkmsvs.com for more details.
• Please provide following information in the resume for immediate processing
• Reasons for leaving current and/or last employment
• Last drawn and/or current salary
• Expected salary
• Date of availability and/or Notice Period
• All applications will be treated in strictest confidence and only shortlisted candidates will be notified
• Wee Wai Dan
• EA License No : 03C5391
• EA Reg No : R22109628

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Company Intel

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