Principal Design Verification Engineer

Requirements

• Strong academic and technical background in electrical engineering. At minimum, a Bachelor's in EE is
• required, and a Maser's is preferred.
• ≥8 years' experience supporting or developing complex SoC/silicon products for Server, Storage, and/or
• Networking applications.
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for
• customer meetings in advance, and to work with minimal guidance and supervision.
• Entrepreneurial, open-mind behavior and can-do attitude. Think and act fast with the customer in mind!
• Authorized to work in Canada and start immediately.
• Required Experience:
• Experience with integrating C/C++ in System Verilog environments using DPI/PLI
• Ability to use scripting tools (Perl/Python) to automate verification infrastructure.
• Experience in developing infrastructure and tests in a hybrid directed and constrained random
• environments
• Must be able to work independently to develop test-plans, and related test-sequences in UVM to
• generate stimuli and work collaboratively with RTL designers to debug failures.
• Develop user-controlled random constraints in transaction-based verification methodology. Experience
• writing assertions, cover properties and analyzing coverage data
• Must have prior experience using Verification IPs from 3rd party vendors for communication protocols
• such as PCI-Express (Gen-3 and above), Ethernet, Infiniband, DDR, NVMe, USB, etc.
• Develop VIP abstraction layers to simplify and scale verification deployments
• Preferred Experience:
• S/W debugging for SoC based designs in the area of kernel/device-drivers/u-boot
• Physical Layer, Link Layer and Transaction Layer verification expertise in PCIe protocol.
• Experience in memory technologies like DDR4/DDR5/HBM.
• Experience with FPGA-based verification/emulation.
• Base salary range is $165,000 CAD -$210,000 CAD, and will be determined based on the candidate's capabilities and employees in similar positions.

Benefits

Additional Information

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Job Description We are looking for a Principal Design Verification Engineer with proven experience in all aspects of verification in UVM and C/C++. The candidate must have experience using high level programming languages such as C/C++ to communicate with System Verilog and/or UVM based environments to aid RTL simulation, CoSimulation and Emulation.

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