Full-Chip Physical Design Engineer

Requirements

• Bachelor's or Master's degree in Electrical Engineering or Computer Science.
• Minimum of 3 years of experience in ASIC design and verification.
• Experience in deep submicron CMOS technologies.
• Comprehensive knowledge of the full design cycle from RTL to GDSII.
• Experience in RTL2GDS flow, floorplanning, and power planning.
• Proficiency in PnR tools such as Synopsys or Cadence.
• Strong scripting skills for automation and efficiency improvements.
• Experience with chip-level design planning, partitioning, and feedthrough management.
• Ability to collaborate with IP teams for the physical integration of analog IPs.
• Experience working with multi-functional teams (package and power integrity) to ensure successful bump and PG planning.
• Why Cisco?
• We are Cisco, and our power starts with you.

Additional Information

Meet the Team Step into Cisco's ASIC Physical Design Team, where innovation meets collaboration. As a group of highly skilled engineers, we're redefining what's possible in silicon technology. Our mission is to drive the future of chip design, managing full-chip physical implementation from RTL to GDSII and beyond. Working hand-in-hand with Front-End teams, we transform cutting-edge designs into industry-leading silicon solutions. Together, we're building the foundation for the future of connectivity, driving advancements in power, performance, and reliability with every project.

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Company Intel

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