IC Design Engineer (DFT)

Responsibilities

• Participate in chip level DFT architecture definition.
• Implement basic DFT schemes, including scan, boundary scan, MBIST, Logic BIST and SSN
• Verify all DFT logics and test patterns with simulation
• Test modes static timing analysis
• Participate in ATE bring-up and debug the DFT patterns on ATE.
• Requirements/Qualifications:
• Either Bachelor or Master degree, 5+ years related experience required.
• Good understanding of the General DFT methodology such as BIST, SCAN, JTAG and ATPG
• Be familiar with basic Mentor/ Synopsys DFT flow and tools
• Experience in developing constraints for synthesis/STA
• Multi-mode, multi-corner STA experience, Understanding Sign-Off Checks
• Education/Certifications
• Preferred Degree: MS Preferred Major: Microelectronics or related discipline
• If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

Additional Information

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: Broadcom offers an excellent opportunity to contribute to a team environment and to grow personal career path. You will be working with internal and external customers to develop state of the art IC solutions utilizing Broadcom's leading edge CMOS cell-based ASIC technologies. You will have responsibility for ASIC designs through all of the key development and implementation phases including RTL analysis, synthesis, design optimization, timing verification, simulation, test insertion, physical design, vector generation, and post-prototype test support. Candidates will have opportunity to work on the latest 5nm/3nm designs

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