ASIC Engineering Technical Lead - DFT

Responsibilities

• We are seeking a motivated, proactive, and intellectually curious ASIC Engineering Technical Leader with focus in Design-for-Test. In this role, you will be leading development of DFT solutions for next-generation ASICs for multi-100G to 1.6T coherent optical communications products.
• Lead implementation of SSN, hierarchical test flow DFT architectures, including scan insertion, compression/decompression logic, memory BIST, and logic BIST, using Siemens Tessent, or Synopsys, tools for RTL and gate netlist DFT implementation.
• Generate and deliver ATPG test pattern for stuck-at, transition, cell aware and path delay fault models, drive scan-based diagnosis methodology for Silicon failure debug, and provide post-silicon testing and validation support
• Responsible for evaluating design readiness for scan insertion through RTL and physical design Scan Design Rule Check (DRC) tools
• Integration and verification of Design for Test (DFT) fabrics and IP within Subsystems
• Perform simulation runs and debug for non-timing and back annotated timing (SDF) gate level simulations
• Develop test scripts, automate processes, and analyze data using programming languages such as Python, Tcl, or C++

Requirements

• Bachelors + 8 years of related experience, or Masters + 6 years of related experience, or PhD + 3 years of related experience
• Prior experience working with ASICs
• Prior experience in scan insertion and DFT setup, integration and validation
• Prior experience implementing DFT architectures-including scan insertion, compression/decompression logic, and memory/logic BIST.
• 10+ years of experience working with ASICs
• 10+ years of experience in scan insertion and DFT setup, integration and validation
• Experience driving ASIC DFT execution from concept through tapeout
• Experience working with ATE testers and test teams
• RTL experience to understand and debugging issues pertaining to DFT
• Ability to solve complex problems including clock domain crossings
• Familiar with advanced silicon process and technology nodes for high speed and low power consumption
• Strong implementation or integration of design blocks using Verilog/System Verilog
• Why Cisco?
• We are Cisco, and our power starts with you.
• Message to applicants applying to work in the U.S. and/or Canada:
• The starting salary range posted for this position is $183,800.00 to $263,600.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.

Benefits

Additional Information

The application window is expected to close on: 06/30/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received . Meet the Team Acacia, part of Cisco, provides innovative silicon-based high-speed optical interconnect products to accelerate network scalability through advancements in performance, capacity, and cost. Our DSP ASICs, silicon photonic PICs, and coherent modules empower cloud and service providers to meet the fast-growing demand for data. We have assembled a team of cross-functional experts capable of solving the challenges of next-generation optical interconnects, resulting in industry-leading, award-winning products. Come join us at Cisco, named the #1 world's best workplaces, and do purposeful work that makes a global impact and gives back to a company culture that empowers an inclusive future for all.

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