ASIC Engineer

Responsibilities

• Design and optimize advanced SRAM / TCAM macro layouts for next-generation products.
• Ensure DRC/LVS/ERC signoff and drive first-pass silicon success.
• Collaborate with circuit, verification, and physical design teams to resolve layout issues and integrate solutions.
• Promote layout best practices and support innovation on leading-edge process nodes.
• Mentor junior team members and help achieve key project milestones.

Requirements

• Bachelor's degree in Electrical Engineering, Computer Science, or a related field.
• 5+ years of professional experience in embedded memory layout.
• Proficiency with the Virtuoso layout editor (or other similar EDA tool)
• Experience with physical verification tools such as Calibre (DRC/LVS/ERC) or other similar tool
• Strong communication skills and a positive mindset.
• Master's degree in Electrical Engineering, Computer Science, or a related field.
• Experience working with advanced technology nodes.
• Demonstrated ability to collaborate effectively in cross-functional teams.
• Proven track record of successful project delivery in embedded memory layout.
• We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.
• Why Cisco?
• We are Cisco, and our power starts with you.

Additional Information

Meet the Team Join the Cisco Silicon One team in developing essential building blocks for web-scale and service provider networks. Our SRAM / TCAM design team unites a circuit architect, circuit designer, CAD engineer, and manager, each bringing specialized expertise to create advanced memory solutions. We focus on technical excellence, streamlined processes, and open collaboration to deliver robust SRAM / TCAM designs and meet ambitious project goals. Committed to innovation and teamwork, we tackle complex challenges and drive the future of memory technology together.

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Company Intel

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