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ASIC/SOC Silicon Physical Design Engineer

External
matx logoMatx · Mountain View, CA
$120K–$250K/yrFull-timeOn-site1mo ago
CompliancePerlPython
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Requirements

  • Bachelor of Science in Electrical Engineering or equivalent
  • Minimum 8 years of industry experience in ASIC Physical Design
  • Great interpersonal and communication skills
  • Strong proficiency in programming languages such as Perl, Python, and TCL
  • Expertise driving Physical Design construction and sign-off for blocks, subsystems, and/or fullchip from early RTL to production silicon
  • Experience collaborating with Design, Verification, and DFT teams to structure, partition, and optimize designs for PPA through sign-off
  • Bonus Points If You Have
  • 8 years of industry experience in ASIC Physical Design
  • Experience working with third-party Design Services partners

Benefits

The US base salary for this full-time position is determined based on a variety of factors including role, experience, location, job related skills, and relevant education and training. Career length is only a guideline for compensation.Early Career - $120,000 - $250,000 + equityMid Career - $175,000 - $362,500 + equitySenior Career - $250,000 - $475,000 + equityA Stake in our success A cash/equity mix that fits your needs and option to do early exerciseHeath & Wellness Company subsidized Health, Dental, Vision, and Life insurance; Pre-tax Health Savings Accounts with generous company contribution (even if you don't)Time To Recharge 4 weeks paid time off (accrued), 12 company holidays, and 3 weeks remote/flexible work per yearSupport to Parents Up to 12 weeks of paid parental leave, regardless of your path to parenthoodLearning & Development $1,500 yearly towards your professional development e.g. conferences, courses, and other learning opportunitiesTeam Connection Team Lunches, quarterly off-sites, and regular town hallsFinancial Wellbeing 401K and/or Roth IRA, with 5% company contribution, even if you don't!Flexible Spending Accounts Pre-tax spend accounts for medical, dental/vision, dependent care, parking, and transit expensesCommute On Us For those commuting up to 1 hour, put your rideshare cost on our company card and reclaim the drive-time to get work done!MatX E[x]tras $50 per month to use on the perks you care about mostRemote Perks We work remotely Monday & Friday, supported by home-tech setup, and remote wifi expense reimbursementAll candidates must be authorized to work in the United States and work from our offices in Mountain View Tuesdays-Thursdays.This position requires access to information that is subject to U.S. export controls. This offer of employment is contingent upon the applicants capacity to perform job functions in compliance with U.S. export control laws without obtaining a license from U.S. export control authorities.Health insuranceDental insuranceVision insurance401(k)Remote work optionsFlexible scheduleEquity / stock optionsPerformance bonusParental leave

Additional Information

What MatX Is Building MatX's mission is to make the world's best AI models run as efficiently as allowed by physics, bringing the world years ahead in AI quality and availability. MatX is seeking silicon physical design engineers to join our team as we create best-in-class silicon for high-performance and sustainable GenAI. Silicon Physical Design Engineers will be responsible for developing performant and functionally correct silicon for MatX products across compute, memory management, high-speed connectivity, and other key technologies in leading-edge process nodes. What You'll Do Here Contribute to MatX's Physical Design methodology to achieve a scalable solution across block, subsystem, and fullchip designs from RTL to GDSII Own entire subsystems or subsets and/or chip-level Physical Design deliverables including but not limited to: construction (partitioning, floorplanning, synthesis, place & route, clocking) and sign-off (equivalency, extraction, timing, power estimation, EMIR, physical verification) Plan and drive intermediate and sign-off reviews. Report execution progress towards various silicon milestones including design freeze and tapeout Work closely with the Design, DFT, and other Physical Design co-owners of the subsystem/block in question to deliver best-in-class Performance-Power-Area results

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