Sr Applied Scientist, ML Codesign, Edge AI Platform

About the role

Amazon's Devices and Services organization has shipped multiple generations of first-party silicon for consumer devices. The differentiating intellectual property across this portfolio is a custom machine learning processor co-designed with the compression algorithms it runs. This role sits at the intersection of three teams. The Applied Science team produces compressed model checkpoints. The Silicon Engineering team designs the Application-Specific Integrated Circuits (ASICs). The Compiler and Runtime team lowers compressed models to silicon. You will be the Sr. architect who closes the loop across all three.

Requirements

• 3+ years of building machine learning models for business application experience
• PhD, or Master's degree and 6+ years of applied research experience
• Experience programming in Java, C++, Python or related language
• Experience with neural deep learning methods and machine learning
• Experience with modeling tools such as R, scikit-learn, Spark MLLib, MxNet, Tensorflow, numpy, scipy etc.
• Experience with large scale distributed systems such as Hadoop, Spark etc.
• Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status.
• Our inclusive culture empowers Amazonians to deliver the best results for our customers. If

Additional Information

Define the joint optimization of model compression and silicon architecture for Amazon's next generation of edge and cloud inference accelerators. Your work will set the technical targets that propagate across the model, compiler, runtime, and silicon stack. We are hiring a Sr. Applied Scientist to be the technical leader who closes the loop between compression science and silicon design. Today's generation ships advanced quantization and large-model distillation in production, running multi-billion parameter language models at inference economics typical of much larger systems. Future generations target significantly larger models at the edge and in the cloud. You will be a senior architect of the next-generation accelerator and of the compression algorithms it executes natively. Few roles in the industry let one technical leader influence the model, the compiler, the runtime, and the silicon without organizational friction. This is one of them. You have spent the last several years thinking about why hardware decisions and accuracy decisions live in different teams, and you want to be the person who owns both. You have published at MLSys, ISCA, MICRO, NeurIPS, or ICML on quantization, pruning, or hardware-aware training, and you want your next paper to ship in a chip rather than in a benchmark suite. You want a vertical stack-model, compression, compiler, runtime, operating system, silicon-where the same engineering organization owns every layer and a sr. architect can move all of them. Key job responsibilities - Define the hardware-aware compression roadmap for next-generation accelerators, working backward from accuracy targets on standard language and reasoning benchmarks including Massive Multitask Language Understanding (MMLU), GSM8K, HumanEval, and Instruction Following Evaluation (IFEval). - Own the joint optimization of compression algorithms (post-training quantization, quantization-aware training, knowledge distillation, structured pruning) with the underlying hardware. - Represent applied science in silicon architecture reviews and influence decisions across the memory and compute subsystems of the accelerator. - Set the science roadmap for the compression techniques the next architecture must support; validate that compression algorithms achieve target accuracy on the benchmarks our products are evaluated against. - Mentor a team of senior and mid-level applied scientists working on compression and hardware-aware training. - Serve as a single-threaded technical leader for the codesign agenda, accountable to senior leadership review.

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