Senior Principal Engineer, Chip Lead, Photonic Fabric Chiplet

Responsibilities

• Own the end ‑ to ‑ end product design s panning Electrical IC , Photonic IC, f irmware stack , and a dvanced packaging design.
• Lead micro ‑ architecture and RTL development for the Electrical IC that can include high speed SERDES and digital subsystems with internally developed IPs and industry standard external I Ps such as UALink , UCIe , etc.
• Collaborate with v erification team to ensure robust functional and per formance verification spanning digital RTL, AMS and electrical-optical interface s .
• Work closely with physical design and packaging teams on floorplanning , physical implementation, timing, power, and physical verifi cation closure.
• Partner with DFT experts to d rive DFT strategy for digital, analog SERDES, and system ‑ level testability.
• Partner with p hotonics team to define PIC architecture , interfaces, and control schemes , and e nsure robust electrical -optical co ‑ design .
• Collaborate with test engineering to drive ATE enablement , test program development, and debug.
• Identify and communicate technical status, risks, and tradeoffs to engineering and product leadership.

Requirements

• Bachelor's degree in Computer Science , Electrical Engineering , or related fields and 15+ years of related professional experience OR Master's degree / PhD in Computer Science, Electrical Engineering or related fields with 8 -12 years of experience.
• 15+ years of experience in ASIC / SoC development with end ‑ to ‑ end chip ownership .
• Strong experience across Micro ‑ architecture and RTL desig n, h igh ‑ speed analog SERDE S , p hysical design and sign ‑ off , DFT and manufacturing test , a dvanced packaging and chiplet ‑ style integration , p ost ‑ silicon bring ‑ up , ATE, and system validation .
• Ability to clearly articulate architectural and implementation tradeoffs across performance, power, area, yield, cost, schedule, and risk.

Additional Information

About Marvell Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact As Generative AI continues to advance, the performance drivers for data center infrastructure are shifting from systems-on-chip (SOCs) to systems of chips. In the era of Accelerated Computing, data center bottlenecks are no longer limited to compute performance, but rather the system's interconnect bandwidth, memory bandwidth, and memory capacity. The Photonic Fabric™ is the next-generation interconnect technology that delivers a tenfold increase in performance and energy efficiency compared to competing solutions. The Photonic Fabric™ includes optical interface chiplets, optical interposers, and Optical Multi-chip Interconnect Bridges (OMIB). This allows customers to easily incorporate high bandwidth, low power, and low latency optical interfaces into their AI accelerators and GPUs. The technology is fully compatible with both protocol and physical layers, including standard 2.5D packaging processes. This seamless integration enables XPUs to utilize optical interconnects for both compute-to-compute and compute-to-memory fabrics, achieving bandwidths in the tens of terabits per second with nanosecond latencies. This innovation empowers hyperscalers to enhance the efficiency and cost-effectiveness of AI processing by optimizing the XPUs required for training and inference, while significantly reducing the TCO2 impact. What You Can Expect Marvell Technology is seeking a highly experienced Chip Lead to own the end ‑ to ‑ end development of a heterogeneous photonic chiplet comprising a high ‑ speed electrical IC with advanced analog SERDES and a photonic integrated circuit (PIC) , brought together using advanced co ‑ packaged technologies . This role requires technical breadth across mixed ‑ signal SoC design, photonic integration, chiplet ‑ style partitioning, firmware and package ‑ level co ‑ design , along with proven leadership delivering complex silicon from concept through silicon bring ‑ up , ATE, and system validation . The ideal candidate has shipped high ‑ speed I/O and/or optical products , understands electrical ‑ optical tradeoffs, and can act as the single technical owner across die, package, optics, and system boundaries.

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