Senior ASIC Design/Verification Engineer
External
Code Metal · San Franscisco HubPrepare for this interview
EliteAI-generated questions, company research, and talking points tailored to this role
Responsibilities
- Architect Agentic AI Pipelines: Partner with AI and software teams to automate the generation, refinement, and validation of RTL models.
- Optimize Development Velocity: Build robust infrastructure to streamline emulation workloads, significantly reducing turnaround times and hardware development cycles.
- Orchestrate EDA Integration: Drive AI-driven modeling workflows within industry-standard EDA environments to accelerate simulation, emulation, and synthesis.
Requirements
- Education & Experience: M.S. with 3+ years or B.S. with 5+ years of industry experience in the semiconductor domain.
- Deep Silicon Bringup Expertise: 3+ years of extensive experience in full-chip bring up and sophisticated RTL debug using advanced tools such as Verdi, nWave, SimVision, Verisium, or Visualizer.
- Architecture & Design Fundamentals: Solid grasp of digital design, SoC architecture, and mastery of SystemVerilog/Verilog.
- Protocol Proficiency: Deep understanding of high-speed and debug protocols and interfaces, including PCIe, DDR, AXI, I2C, UART, JTAG, etc.
- Testbench Innovation: Experience implementing scalable testbenches for complex multi-die/chiplet environments, utilizing advanced transactors and performance monitors.
- Emulation/Prototyping: Some knowledge and experience in SoC or IP emulation or FPGA prototyping using industry-standard platforms (e.g., Synopsys ZeBu/HAPS, Cadence Palladium/Protium, or Siemens EDA Veloce).
- Automation & Tooling: Expert-level proficiency in scripting (Python, Tcl, Bash/tcsh, Makefile) to build and maintain automation frameworks that boost productivity.
- Disciplined Execution: Exceptional ability to plan and execute structured experiments (DoE), perform data-driven analysis, and synthesize complex findings for stakeholders.
- Preferred Qualifications (Bonus)
- AI/SW Collaboration: Proven track record of cross-functional collaboration with software teams to refine and maintain agentive AI workflows.
Benefits
Additional Information
About Code Metal Code Metal is redefining code translation for mission-critical industries, helping defense partners move more quickly and reliably from algorithm to silicon. Our platform accelerates deployment of DSP, RF, communications, and embedded signal processing algorithms onto heterogeneous compute targets, including GPUs, FPGAs, ASICs, and edge SoCs. We also support automotive, aerospace, and semiconductor partners deploying complex algorithms onto constrained hardware with speed and rigor. About Code Metal Code Metal is building the future of code transformation. Our platform enables seamless source-to-source transpilation, helping teams translate and optimize software across programming languages and domains. By combining deep expertise in compilers with modern AI-driven pipelines, we are unlocking powerful new ways to accelerate hardware and software development. We are looking for a Senior ASIC Design/Verification Engineer to help expand our core product into the world of AI-assisted hardware design and SystemC modeling. This is a unique opportunity to shape how advanced AI workflows integrate with EDA tools and chip design processes.
Your Match
How well this role fits your profile.
Company Intel
What employees say
Worked at Code Metal? Share your experience