Packaging Engineer (Substrate Design and Layout, Only open for fresh graduate)

Requirements

• Experience with any EDA or CAD design software (e.g., Cadence, AutoCAD, Altium, Mentor) is preferred; candidates without prior experience but with strong learning motivation are also welcome.
• Strong analytical and problem‑solving abilities to support engineering tasks and development activities.
• Ability to organize and prepare technical documentation and follow design guidelines and operational procedures.
• Capability to collaborate with global teams and interface with external suppliers, with an understanding of manufacturing and process requirements.

Additional Information

Participate in the development of package design and advanced substrate layout for products. Learn and become proficient in EDA layout tools (e.g., Cadence SIP/Allegro) to perform package and substrate drawing, design modifications, and related engineering tasks. Perform basic routing planning, layer stack‑up configuration, and design‑for‑manufacturability (DFM) checks based on established design rules and manufacturing requirements. Collaborate with cross‑functional engineering teams-including hardware, manufacturing, and packaging-to support package structure evaluations, design updates, and issue resolution. Required Qualifications: Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Materials Science, Mechanical Engineering, Physics, or other related engineering/science fields. Coursework, project experience, or internships related to semiconductor packaging, electronics design, PCB/substrate design, or similar areas are preferred but not required. Strong willingness to learn and ability to quickly grasp package design workflows, substrate layout methodologies, and relevant EDA tools. Effective communication and teamwork skills, with the ability to work collaboratively in cross‑functional environments.

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Company Intel

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