Senior Staff, Design Verification Engineer

Requirements

• Minimum:
• BS in Electrical Engineering, Computer Science or related field with 12 + years of Industry experience or MS Electrical Engineering, Computer Science or related field preferred with 7 + years industry experience.
• Experience in SoC verification cycle from architecture to tape out to bring up.
• Good knowledge of verification methodologies such as UVM/OVM etc.
• Hands on ASIC-SoC Design verification tests and debug experience.
• Fluency with SystemVerilog randomization constraints, coverage, and assertions methodology.
• Good problem-solving skills, and the passion to take on challenges (particularly in AI domain).
• Good experience with SystemVerilog, and verification methodology (UVM/OVM/VMM).
• Passionate about AI and thriving in a fast-paced and dynamic startup culture.
• Preferred:
• Experience with C/C++, SystemC (a big plus!)
• Successfully lead creation/implementation of multiple SoC verification environments and tape out efforts.
• Equal Opportunity Employment Policy

Additional Information

At d-Matrix , we are focused on unleashing the potential of generative AI to power the transformation of technology. We are at the forefront of software and hardware innovation, pushing the boundaries of what is possible. Our culture is one of respect and collaboration. We value humility and believe in direct communication. Our team is inclusive , and our differing perspectives allow for better solutions. We are seeking individuals passionate about tackling challenges and are driven by execution. Ready to come find your playground? Together , we can help shape the endless possibilities of AI. Location: Hybrid, working onsite at our Santa Clara, CA headquarters 3 days per week. The role: Design Verification Engineer, Senior Staff

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Company Intel

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